📄 ks_def.h
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/* ---------------------------------------------------------------------------
Copyright (c) 2004-2006 Micrel, Inc. All rights reserved.
---------------------------------------------------------------------------
ks_def.h - KS884X switch definitions.
Author Date Version Description
THa 02/28/06 Do not use HW_WRITE_BYTE because of limitation of
some hardware platforms.
THa 02/23/06 Removed KS884X_HW conditional.
PCD 04/29/05 0.1.3 Correct reset device function, and check device ID for device.
THa 02/13/04 Created file.
THa 10/05/04 Updated for PCI version.
THa 10/14/04 Updated with latest specs.
---------------------------------------------------------------------------
*/
#ifndef __KS_DEF_H
#define __KS_DEF_H
#if 0
#define DEVELOP
#endif
/* -------------------------------------------------------------------------- */
#define TO_LO_BYTE( x ) (( UCHAR )(( x ) >> 8 ))
#define TO_HI_BYTE( x ) (( USHORT )(( x ) << 8 ))
/* KS884X byte registers */
#define REG_FAMILY_ID 0x88
/* SIDER */
#define REG_CHIP_ID_41 0x8810
#define REG_CHIP_ID_42 0x8800
#define SWITCH_CHIP_ID_MASK_41 0xFF10
#define SWITCH_CHIP_ID_MASK 0xFFF0
#define SWITCH_CHIP_ID_SHIFT 4
#define SWITCH_REVISION_MASK 0x000E
#define SWITCH_START 0x01
#define CHIP_IP_41_ISA 0x8810
#define CHIP_IP_42_ISA 0x8800
#define CHIP_IP_61_ISA 0x8890
#define CHIP_IP_62_ISA 0x8880
#define CHIP_IP_41_PCI 0x8850
#define CHIP_IP_42_PCI 0x8840
#define CHIP_IP_61_PCI 0x88D0
#define CHIP_IP_62_PCI 0x88C0
/* SGCR1 */
#define REG_SWITCH_CTRL_1 0x02
#define SWITCH_NEW_BACKOFF 0x80
#define SWITCH_802_1P_MASK 0x70
#define SWITCH_802_1P_BASE 7
#define SWITCH_802_1P_SHIFT 4
#define SWITCH_PASS_PAUSE 0x08
#define SWITCH_BUFFER_SHARE 0x04
#define SWITCH_RECEIVE_PAUSE 0x02
#define SWITCH_LINK_AGE 0x01
#define REG_SWITCH_CTRL_1_HI 0x03
#define SWITCH_PASS_ALL 0x80
#define SWITCH_TX_FLOW_CTRL 0x20
#define SWITCH_RX_FLOW_CTRL 0x10
#define SWITCH_CHECK_LENGTH 0x08
#define SWITCH_AGING_ENABLE 0x04
#define SWITCH_FAST_AGE 0x02
#define SWITCH_AGGR_BACKOFF 0x01
/* SGCR2 */
#define REG_SWITCH_CTRL_2 0x04
#define UNICAST_VLAN_BOUNDARY 0x80
#define MULTICAST_STORM_DISABLE 0x40
#define SWITCH_BACK_PRESSURE 0x20
#define FAIR_FLOW_CTRL 0x10
#define NO_EXC_COLLISION_DROP 0x08
#define SWITCH_HUGE_PACKET 0x04
#define SWITCH_LEGAL_PACKET 0x02
#define SWITCH_BUF_RESERVE 0x01
#define REG_SWITCH_CTRL_2_HI 0x05
#define SWITCH_VLAN_ENABLE 0x80
#define SWITCH_IGMP_SNOOP 0x40
#define PRIORITY_SCHEME_SELECT 0x0C
#define PRIORITY_RATIO_HIGH 0x00
#define PRIORITY_RATIO_10 0x04
#define PRIORITY_RATIO_5 0x08
#define PRIORITY_RATIO_2 0x0C
#define SWITCH_MIRROR_RX_TX 0x01
/* SGCR3 */
#define REG_SWITCH_CTRL_3 0x06
#define SWITCH_REPEATER 0x80
#define SWITCH_HALF_DUPLEX 0x40
#define SWITCH_FLOW_CTRL 0x20
#define SWITCH_10_MBIT 0x10
#define SWITCH_REPLACE_VID 0x08
#define BROADCAST_STORM_RATE_HI 0x07
#define REG_SWITCH_CTRL_3_HI 0x07
#define BROADCAST_STORM_RATE_LO 0xFF
#define BROADCAST_STORM_RATE 0x07FF
/* SGCR4 */
#define REG_SWITCH_CTRL_4 0x08
/* SGCR5 */
#define REG_SWITCH_CTRL_5 0x0A
#define PHY_POWER_SAVE 0x40
#define CRC_DROP 0x20
#define LED_MODE 0x02
#define TPID_MODE_ENABLE 0x01
/* SGCR6 */
#define REG_SWITCH_CTRL_6 0x0C
#define SWITCH_802_1P_MAP_MASK 3
#define SWITCH_802_1P_MAP_SHIFT 2
/* SGCR7 */
#define REG_SWITCH_CTRL_7 0x0E
/* P1CR1 */
#define REG_PORT_1_CTRL_1 0x10
/* P2CR1 */
#define REG_PORT_2_CTRL_1 0x20
/* P3CR1 */
#define REG_PORT_3_CTRL_1 0x30
#define PORT_BROADCAST_STORM 0x80
#define PORT_DIFFSERV_ENABLE 0x40
#define PORT_802_1P_ENABLE 0x20
#define PORT_BASED_PRIORITY_MASK 0x18
#define PORT_BASED_PRIORITY_BASE 0x03
#define PORT_BASED_PRIORITY_SHIFT 3
#define PORT_PORT_PRIORITY_0 0x00
#define PORT_PORT_PRIORITY_1 0x08
#define PORT_PORT_PRIORITY_2 0x10
#define PORT_PORT_PRIORITY_3 0x18
#define PORT_INSERT_TAG 0x04
#define PORT_REMOVE_TAG 0x02
#define PORT_PRIORITY_ENABLE 0x01
/* P1CR2 */
#define REG_PORT_1_CTRL_2 0x11
/* P2CR2 */
#define REG_PORT_2_CTRL_2 0x21
/* P3CR2 */
#define REG_PORT_3_CTRL_2 0x31
#define PORT_MIRROR_SNIFFER 0x80
#define PORT_MIRROR_RX 0x40
#define PORT_MIRROR_TX 0x20
#define PORT_DOUBLE_TAG 0x10
#define PORT_802_1P_REMAPPING 0x08
#define PORT_VLAN_MEMBERSHIP 0x07
#define REG_PORT_1_CTRL_2_HI 0x12
#define REG_PORT_2_CTRL_2_HI 0x22
#define REG_PORT_3_CTRL_2_HI 0x32
#define PORT_REMOTE_LOOPBACK 0x80
#define PORT_INGRESS_FILTER 0x40
#define PORT_DISCARD_NON_VID 0x20
#define PORT_FORCE_FLOW_CTRL 0x10
#define PORT_BACK_PRESSURE 0x08
#define PORT_TX_ENABLE 0x04
#define PORT_RX_ENABLE 0x02
#define PORT_LEARN_DISABLE 0x01
/* P1VIDCR */
#define REG_PORT_1_CTRL_VID 0x13
/* P2VIDCR */
#define REG_PORT_2_CTRL_VID 0x23
/* P3VIDCR */
#define REG_PORT_3_CTRL_VID 0x33
#define PORT_DEFAULT_VID 0xFFFF
/* P1CR3 */
#define REG_PORT_1_CTRL_3 0x15
/* P2CR3 */
#define REG_PORT_2_CTRL_3 0x25
/* P3CR3 */
#define REG_PORT_3_CTRL_3 0x35
#define PORT_USER_PRIORITY_CEILING 0x10
#define PORT_INGRESS_LIMIT_MODE 0x0C
#define PORT_INGRESS_ALL 0x00
#define PORT_INGRESS_UNICAST 0x04
#define PORT_INGRESS_MULTICAST 0x08
#define PORT_INGRESS_BROADCAST 0x0C
#define PORT_COUNT_IFG 0x02
#define PORT_COUNT_PREAMBLE 0x01
/* P1IRCR */
#define REG_PORT_1_IN_RATE 0x16
/* P1ERCR */
#define REG_PORT_1_OUT_RATE 0x18
/* P2IRCR */
#define REG_PORT_2_IN_RATE 0x26
/* P2ERCR */
#define REG_PORT_2_OUT_RATE 0x28
/* P3IRCR */
#define REG_PORT_3_IN_RATE 0x36
/* P3ERCR */
#define REG_PORT_3_OUT_RATE 0x38
#define PORT_PRIORITY_RATE 0x0F
#define PORT_PRIORITY_RATE_SHIFT 4
#define REG_PORT_1_LINK_MD_CTRL 0x1A
/* P1SCSLMD */
#define REG_PORT_1_LINK_MD_RESULT 0x1B
#define REG_PORT_2_LINK_MD_CTRL 0x2A
/* P2SCSLMD */
#define REG_PORT_2_LINK_MD_RESULT 0x2B
#define PORT_CABLE_DIAG_RESULT 0x60
#define PORT_CABLE_STAT_NORMAL 0x00
#define PORT_CABLE_STAT_OPEN 0x20
#define PORT_CABLE_STAT_SHORT 0x40
#define PORT_CABLE_STAT_FAILED 0x60
#define PORT_START_CABLE_DIAG 0x10
#define PORT_FORCE_LINK 0x08
#define PORT_POWER_SAVING 0x04
#define PORT_PHY_REMOTE_LOOPBACK 0x02
#define PORT_CABLE_FAULT_COUNTER_H 0x01
#define PORT_CABLE_FAULT_COUNTER_L 0xFF
#define PORT_CABLE_FAULT_COUNTER 0x1FF
/* P1CR4 */
#define REG_PORT_1_CTRL_4 0x1C
/* P2CR4 */
#define REG_PORT_2_CTRL_4 0x2C
#define PORT_AUTO_NEG_ENABLE 0x80
#define PORT_FORCE_100_MBIT 0x40
#define PORT_FORCE_FULL_DUPLEX 0x20
#define PORT_AUTO_NEG_SYM_PAUSE 0x10
#define PORT_AUTO_NEG_100BTX_FD 0x08
#define PORT_AUTO_NEG_100BTX 0x04
#define PORT_AUTO_NEG_10BT_FD 0x02
#define PORT_AUTO_NEG_10BT 0x01
#define REG_PORT_1_CTRL_4_HI 0x1D
#define REG_PORT_2_CTRL_4_HI 0x2D
#define PORT_LED_OFF 0x80
#define PORT_TX_DISABLE 0x40
#define PORT_AUTO_NEG_RESTART 0x20
#define PORT_REMOTE_FAULT_DISABLE 0x10
#define PORT_POWER_DOWN 0x08
#define PORT_AUTO_MDIX_DISABLE 0x04
#define PORT_FORCE_MDIX 0x02
#define PORT_LOOPBACK 0x01
/* P1SR */
#define REG_PORT_1_STATUS 0x1E
/* P2SR */
#define REG_PORT_2_STATUS 0x2E
#define PORT_MDIX_STATUS 0x80
#define PORT_AUTO_NEG_COMPLETE 0x40
#define PORT_STATUS_LINK_GOOD 0x20
#define PORT_REMOTE_SYM_PAUSE 0x10
#define PORT_REMOTE_100BTX_FD 0x08
#define PORT_REMOTE_100BTX 0x04
#define PORT_REMOTE_10BT_FD 0x02
#define PORT_REMOTE_10BT 0x01
#define REG_PORT_1_STATUS_HI 0x1F
#define REG_PORT_2_STATUS_HI 0x2F
#define REG_PORT_3_STATUS_HI 0x3F
#define PORT_HP_MDIX 0x80
#define PORT_REVERSED_POLARITY 0x20
#define PORT_RX_FLOW_CTRL 0x10
#define PORT_TX_FLOW_CTRL 0x08
#define PORT_STAT_SPEED_100MBIT 0x04
#define PORT_STAT_FULL_DUPLEX 0x02
#define PORT_REMOTE_FAULT 0x01
#define REG_MEDIA_CONV_PHY_ADDR 0x40
/* TOSR1 */
#define REG_TOS_PRIORITY_CTRL_1 0x60
/* TOSR2 */
#define REG_TOS_PRIORITY_CTRL_2 0x62
/* TOSR3 */
#define REG_TOS_PRIORITY_CTRL_3 0x64
/* TOSR4 */
#define REG_TOS_PRIORITY_CTRL_4 0x66
/* TOSR5 */
#define REG_TOS_PRIORITY_CTRL_5 0x68
/* TOSR6 */
#define REG_TOS_PRIORITY_CTRL_6 0x6A
/* TOSR7 */
#define REG_TOS_PRIORITY_CTRL_7 0x6C
/* TOSR8 */
#define REG_TOS_PRIORITY_CTRL_8 0x6E
#define TOS_PRIORITY_MASK 3
#define TOS_PRIORITY_SHIFT 2
/* MACAR1 */
#define REG_MAC_ADDR_0 0x70
#define REG_MAC_ADDR_1 0x71
/* MACAR2 */
#define REG_MAC_ADDR_2 0x72
#define REG_MAC_ADDR_3 0x73
/* MACAR3 */
#define REG_MAC_ADDR_4 0x74
#define REG_MAC_ADDR_5 0x75
#define REG_USER_DEFINED_0 0x76
#define REG_USER_DEFINED_1 0x77
#define REG_USER_DEFINED_2 0x78
/* IACR */
#define REG_INDIRECT_ACCESS_CTRL_0 0x79
#define REG_INDIRECT_ACCESS_CTRL_1 0x7A
/* IADR1 */
#define REG_INDIRECT_DATA_8 0x7B
/* IADR3 */
#define REG_INDIRECT_DATA_7 0x7C
#define REG_INDIRECT_DATA_6 0x7D
/* IADR2 */
#define REG_INDIRECT_DATA_5 0x7E
#define REG_INDIRECT_DATA_4 0x7F
/* IADR5 */
#define REG_INDIRECT_DATA_3 0x80
#define REG_INDIRECT_DATA_2 0x81
/* IADR4 */
#define REG_INDIRECT_DATA_1 0x82
#define REG_INDIRECT_DATA_0 0x83
/* PHAR */
/* P1MBCR */
/* P2MBCR */
#define PHY_REG_CTRL 0
#define PHY_RESET 0x8000
#define PHY_LOOPBACK 0x4000
#define PHY_SPEED_100MBIT 0x2000
#define PHY_AUTO_NEG_ENABLE 0x1000
#define PHY_POWER_DOWN 0x0800
#define PHY_MII_DISABLE 0x0400
#define PHY_AUTO_NEG_RESTART 0x0200
#define PHY_FULL_DUPLEX 0x0100
#define PHY_COLLISION_TEST 0x0080
#define PHY_HP_MDIX 0x0020
#define PHY_FORCE_MDIX 0x0010
#define PHY_AUTO_MDIX_DISABLE 0x0008
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