📄 target.h
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#undef DBG
#undef DEBUG_HARDWARE_SETUP
#undef DEBUG_SPEED_SETUP
#undef SH_32BIT_ALIGNED
/*
* Hardware access macros
*/
#ifdef KS_PCI_BUS
/*
* To access device registers through the PCI bus
*
* Note: CSR is mapping to SH7751R PCI memory space by memory mapping.
* The driver will locate device registers as offsets from this base address.
*
* When we access to registers, we need to software byte swap the data and then put it
* on the PCI bus, if big-endian mode is selected for SH7751R PCI controller
* (which is default setting).
*/
#define KS884X_ENDIAN_BIG 1 /* endian mode to access PCI CSR reg, 1:big-endian, 0:little-endian */
#define SWAP_LONG(x) LONGSWAP(x)
#define SWAP_WORD(x) (MSB(x) | LSB(x) << 8)
/*
* Read\Write KS884x Registers
*/
#define HW_READ_BYTE( phwi, addr, data ) \
*(PUCHAR)data = *(volatile PUCHAR)(phwi->m_ulVIoAddr + addr )
#define HW_WRITE_BYTE( phwi, addr, data ) \
*(volatile PUCHAR)(phwi->m_ulVIoAddr + addr ) = (UCHAR) data
#define HW_READ_WORD( phwi, addr, data ) \
if (phwi->m_boardBusEndianMode & KS884X_ENDIAN_BIG) \
{ \
USHORT wDatap; \
wDatap = *(volatile PUSHORT)((phwi)->m_ulVIoAddr + addr ); \
*(PUSHORT)data = SWAP_WORD ( wDatap ); \
} \
else \
*(PUSHORT)data = *(volatile PUSHORT)((phwi)->m_ulVIoAddr + addr );
#define HW_WRITE_WORD( phwi, addr, data ) \
if (phwi->m_boardBusEndianMode & KS884X_ENDIAN_BIG) \
*(volatile PUSHORT)(phwi->m_ulVIoAddr + addr ) = (USHORT)( SWAP_WORD (data) ); \
else \
*(volatile PUSHORT)(phwi->m_ulVIoAddr + addr ) = data;
#define HW_READ_DWORD( phwi, addr, data ) \
if (phwi->m_boardBusEndianMode & KS884X_ENDIAN_BIG) \
{ \
ULONG dwDatap=0; \
dwDatap = *(volatile PULONG)(phwi->m_ulVIoAddr + addr ) ; \
*(PULONG)data = SWAP_LONG ( dwDatap ); \
} \
else \
*(PULONG)data = *(volatile PULONG)(phwi->m_ulVIoAddr + addr );
#define HW_WRITE_DWORD( phwi, addr, data ) \
if (phwi->m_boardBusEndianMode & KS884X_ENDIAN_BIG) \
*(volatile PULONG)(phwi->m_ulVIoAddr + addr ) = (ULONG)( SWAP_LONG (data) ); \
else \
*(volatile PULONG)(phwi->m_ulVIoAddr + addr ) = data;
#define MOVE_MEM( dest, src, len ) \
memcpy( dest, src, len )
/*
* Read\Write KS884x PCI Configuration Space
*/
#define HW_PCI_READ_BYTE( phwi, addr, data ) \
hw_pci_read_byte( phwi, addr, data );
#define HW_PCI_WRITE_BYTE( phwi, addr, data ) \
hw_pci_write_byte( phwi, addr, data );
#define HW_PCI_READ_WORD( phwi, addr, data ) \
hw_pci_read_word( phwi, addr, data );
#define HW_PCI_WRITE_WORD( phwi, addr, data ) \
hw_pci_write_word( phwi, addr, data );
#define HW_PCI_READ_DWORD( phwi, addr, data ) \
hw_pci_read_dword( phwi, addr, data );
#define HW_PCI_WRITE_DWORD( phwi, addr, data ) \
hw_pci_write_dword( phwi, addr, data );
#endif /* #ifdef KS_PCI_BUS */
#ifdef KS_ISA_BUS
/*
* To access device registers through the generic bus
*
* Note: Device registers are mapping to SH7751R CS4 memory space.
* The driver will locate device registers as offsets from this base address.
*
* When we access to registers, we need to software byte swap the data,
* if big-endian mode is selected for SH7751R bus controller.
*/
#define KS884X_ENDIAN_BIG 1 /* endian mode to access PCI CSR reg, 1:big-endian, 0:little-endian */
#undef SH_32BIT_ACCESS_ONLY /* KS8841/2M can be accessed by 32bit data width only */
#define SWAP_LONG(x) LONGSWAP(x)
#define SWAP_WORD(x) (MSB(x) | LSB(x) << 8)
#ifndef SH_32BIT_ACCESS_ONLY
/*
* SH7751R Area4 'Byte Control mode' is enabled,
* SH7751R WE0/WE1/WE2/WE3 are connected to KS8841/2M BE0/BE1/BE2/BE3.
* Area4 can access KS8841/2M by BYTE\WORD\DWORD.
*/
#define HW_READ_BYTE( phwi, addr, data ) \
*(PUCHAR)data = *(volatile PUCHAR)(phwi->m_ulVIoAddr + addr );
#define HW_WRITE_BYTE( phwi, addr, data ) \
*(volatile PUCHAR)(phwi->m_ulVIoAddr + addr ) = (UCHAR) data
#define HW_READ_WORD( phwi, addr, data ) \
if (phwi->m_boardBusEndianMode & KS884X_ENDIAN_BIG) \
{ \
USHORT wDatag; \
wDatag = *(volatile PUSHORT)((phwi)->m_ulVIoAddr + addr ) ; \
*(PUSHORT)data = SWAP_WORD (wDatag ); \
} \
else \
*(PUSHORT)data = *(volatile PUSHORT)((phwi)->m_ulVIoAddr + addr )
#define HW_WRITE_WORD( phwi, addr, data ) \
if (phwi->m_boardBusEndianMode & KS884X_ENDIAN_BIG) \
*(volatile PUSHORT)(phwi->m_ulVIoAddr + addr ) = (USHORT)( SWAP_WORD (data) ); \
else \
*(volatile PUSHORT)(phwi->m_ulVIoAddr + addr ) = data
#else /* ifndef SH_32BIT_ACCESS_ONLY */
/*
* SH7751R Area4 'Byte Control mode' is disabled,
* SH7751R WE0/WE1/WE2/WE3 are not connected to KS8841/2M.
* KS8841/2M BE0/BE1/BE2/BE3 are connected to low.
* Area4 can access KS8841/2M by DWORD only.
* Here, we convert read/write by BYTE/WORD to by DWORD.
*/
#define HW_READ_BYTE( phwi, addr, data ) \
{ \
UCHAR shiftBit; \
ULONG dwDataRead; \
\
switch ( addr & 0x03 ) \
{ \
case 0: \
*(PUCHAR)data = *(volatile PUCHAR)(phwi->m_ulVIoAddr + addr ); \
break; \
default: \
shiftBit=(addr & 0x03) << 3; \
HW_READ_DWORD( phwi, (addr & 0x0C), &dwDataRead ) ; \
*data = (UCHAR)(dwDataRead >>= shiftBit); \
break; \
} \
}
#define HW_WRITE_BYTE( phwi, addr, data ) \
{ \
UCHAR addrByDwordAligned=addr & 0x0C; \
UCHAR shiftBit=(addr & 0x03) << 3; \
ULONG dwDataMask=0xFF; \
ULONG dwDataRead; \
ULONG dwDataWrite=0; \
\
dwDataMask <<= shiftBit; \
HW_READ_DWORD( phwi, addrByDwordAligned, &dwDataRead ) ; \
dwDataRead &= ~dwDataMask ; \
dwDataWrite = ( ( data << shiftBit ) | dwDataRead ); \
HW_WRITE_DWORD( phwi, addrByDwordAligned, dwDataWrite ) ; \
}
#define HW_READ_WORD( phwi, addr, data ) \
{ \
UCHAR shiftBit; \
ULONG dwDataRead; \
\
switch ( addr & 0x03 ) \
{ \
case 0: \
if (phwi->m_boardBusEndianMode & KS884X_ENDIAN_BIG) \
{ \
USHORT wDatag; \
wDatag = *(volatile PUSHORT)((phwi)->m_ulVIoAddr + addr ) ; \
*(PUSHORT)data = SWAP_WORD (wDatag ); \
} \
else \
*(PUSHORT)data = *(volatile PUSHORT)((phwi)->m_ulVIoAddr + addr ); \
break; \
case 2: \
shiftBit=(addr & 0x03) << 3; \
HW_READ_DWORD( phwi, (addr & 0x0C), &dwDataRead ) ; \
*data = (USHORT)(dwDataRead >>= shiftBit); \
break; \
} \
}
#define HW_WRITE_WORD( phwi, addr, data ) \
{ \
UCHAR addrByDwordAligned=addr & 0x0C; \
UCHAR shiftBit=(addr & 0x03) << 3; \
ULONG dwDataMask=0xFFFF; \
ULONG dwDataRead; \
ULONG dwDataWrite=0; \
\
dwDataMask <<= shiftBit; \
HW_READ_DWORD( phwi, addrByDwordAligned, &dwDataRead ) ; \
dwDataRead &= ~dwDataMask ; \
dwDataWrite = ( ( data << shiftBit ) | dwDataRead ); \
HW_WRITE_DWORD( phwi, addrByDwordAligned, dwDataWrite ) ; \
}
#endif /* ifndef SH_32BIT_ACCESS_ONLY */
#define HW_READ_DWORD( phwi, addr, data ) \
if (phwi->m_boardBusEndianMode & KS884X_ENDIAN_BIG) \
{ \
ULONG dwDatag; \
dwDatag = *(volatile PULONG)(phwi->m_ulVIoAddr + addr ) ; \
*(PULONG)data = SWAP_LONG ( dwDatag ); \
} \
else \
*(PULONG)data = *(volatile PULONG)(phwi->m_ulVIoAddr + addr )
#define HW_WRITE_DWORD( phwi, addr, data ) \
if (phwi->m_boardBusEndianMode & KS884X_ENDIAN_BIG) \
*(volatile PULONG)(phwi->m_ulVIoAddr + addr ) = (ULONG)( SWAP_LONG (data) ); \
else \
*(volatile PULONG)(phwi->m_ulVIoAddr + addr ) = data
#define MOVE_MEM( dest, src, len ) \
memcpy( dest, src, len )
#if (0)
#define HW_READ_BUFFER( phwi, addr, data, len ) \
{ \
int lengthInDWord = ((len + 3) >> 2) ; \
PULONG pdwData = (PULONG)data; \
\
HardwareSelectBank( phwi, REG_DATA_BANK ); \
while ( lengthInDWord--) \
*(PULONG)pdwData++ = *(volatile PULONG)(phwi->m_ulVIoAddr + addr ); \
}
#define HW_WRITE_BUFFER( phwi, addr, data, len ) \
{ \
int lengthInDWord = ((len + 3) >> 2) ; \
PULONG pdwData = (PULONG)data; \
\
HardwareSelectBank( phwi, REG_DATA_BANK ); \
while ( lengthInDWord-- ) \
*(volatile PULONG)(phwi->m_ulVIoAddr + addr ) = *pdwData++; \
}
#endif
#define HW_READ_BUFFER( phwi, addr, data, len ) \
{ \
PDMA_XFER pDmaInfo = &phwi->dmaInfo; \
HardwareSelectBank( phwi, REG_DATA_BANK ); \
if ( (pDmaInfo->f_dma_rx) && (len >= pDmaInfo->dma_threshold) ) \
{ \
Platform_DmaStartXfer ( phwi, \
pDmaInfo->dma_rx_channel, \
(ULONG)(phwi->m_ulVIoAddr + addr), \
(ULONG)data, \
(len + 3), \
FALSE) ; \
} \
else \
{ \
int lengthInDWord = ((len + 3) >> 2) ; \
PULONG pdwData = (PULONG)data; \
while ( lengthInDWord-- ) \
*(PULONG)pdwData++ = *(volatile PULONG)(phwi->m_ulVIoAddr + addr );\
} \
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