hardware.c

MICREL 网卡驱动 FOR CE 5.0

#if defined( UNDER_CE ) && defined( SH_BUS ) && defined( DBG )
{
    ULONG dwData;

    NdisRawReadPortUlong( 0xFF800000, &dwData );
    DBG_PRINT( "BCR1=FF800000: %08X"NEWLINE, dwData );
#if 0
    dwData |= 1 << 20;
    DBG_PRINT( "BCR1=FF800000: %08X"NEWLINE, dwData );
    NdisRawWritePortUlong( 0xFF800000, dwData );
#endif

    NdisRawReadPortUshort( 0xFF800004, &RegData );
    DBG_PRINT( "BCR2=FF800004: %04X"NEWLINE, RegData );
#if 0
    RegData |= 3 << 8;
    DBG_PRINT( "BCR2=FF800004: %04X"NEWLINE, RegData );
    NdisRawWritePortUshort( 0xFF800004, RegData );
#endif

    NdisRawReadPortUshort( 0xFF800050, &RegData );
    DBG_PRINT( "BCR3=FF800050: %04X"NEWLINE, RegData );

    NdisRawReadPortUlong( 0xFE0A00F0, &dwData );
    DBG_PRINT( "BCR4=FE0A00F0: %08X"NEWLINE, dwData );

    NdisRawReadPortUlong( 0xFF800008, &dwData );
    DBG_PRINT( "WCR1=FF800008: %08X"NEWLINE, dwData );

    NdisRawReadPortUlong( 0xFF80000C, &dwData );
    DBG_PRINT( "WCR2=FF80000C: %08X"NEWLINE, dwData );

    NdisRawReadPortUlong( 0xFF800010, &dwData );
    DBG_PRINT( "WCR3=FF800010: %08X"NEWLINE, dwData );

    NdisRawReadPortUlong( 0xFE0A0028, &dwData );
    DBG_PRINT( "WCR4=FE0A0028: %08X"NEWLINE, dwData );

#if 0
    HardwareSelectBank( pHardware, 48 );
    HW_READ_DWORD( pHardware, 0, &dwData );
    DBG_PRINT( "%08X"NEWLINE, dwData );
    HW_WRITE_BYTE( pHardware, 3, 0x08 );
    HW_READ_WORD( pHardware, 2, &RegData );
    DBG_PRINT( "%04X"NEWLINE, RegData );
    HW_WRITE_BYTE( pHardware, 2, 0x04 );
    HW_READ_WORD( pHardware, 2, &RegData );
    DBG_PRINT( "%04X"NEWLINE, RegData );
    HW_WRITE_DWORD( pHardware, 0, dwData );
#endif
}
#endif

    /*
     * Set Bus Speed to 125MHz
     */

#ifdef KS_ISA_BUS
    HardwareSelectBank( pHardware, REG_BUS_CTRL_BANK );
#endif

    HW_WRITE_WORD ( pHardware, REG_BUS_CTRL_OFFSET, BUS_SPEED_125_MHZ );

    /*
     * Check ks884x Chip ID
     */

    {

#ifdef KS_ISA_BUS
        HardwareReadRegWord( pHardware,
                             (UCHAR)REG_SWITCH_CTRL_BANK,
                             (UCHAR)REG_CHIP_ID_OFFSET,
                             (PUSHORT)&RegData
                           );
#else
        HW_READ_WORD( pHardware, REG_CHIP_ID_OFFSET, &RegData );

#endif

#ifdef DBG
    DBG_PRINT( "id: %X"NEWLINE, RegData );
#endif

#ifdef DEF_KS8841
        if ( ( RegData & SWITCH_CHIP_ID_MASK_41 ) != REG_CHIP_ID_41 )
#else
        if ( ( RegData & SWITCH_CHIP_ID_MASK_41 ) != REG_CHIP_ID_42 )
#endif
        {

#ifdef DEBUG_COUNTER
            pHardware->m_nBad[ COUNT_BAD_CMD_WRONG_CHIP ]+=1;
#endif
            return FALSE;
        }

#if defined( KS_ISA_BUS )  &&  defined( DBG_ )
        DisplayRegisters( pHardware );
#endif

        return( TRUE );
    }

#ifdef DEBUG_COUNTER
    pHardware->m_nBad[ COUNT_BAD_CMD_INITIALIZE ]+=1;
#endif

    return FALSE;

}  /* HardwareInitialize */


/*
    HardwareReadChipID

    Description:
        This function read family\chip ID, and device revision ID.

    Parameters:
        PHARDWARE pHardware
            Pointer to hardware instance.

    Return: none
*/

void HardwareReadChipID
(
    PHARDWARE pHardware,
    PUSHORT   pChipID,
    PUCHAR    pDevRevisionID
)
{
    USHORT RegData;

    /* Read ks884x Chip ID */

#ifdef KS_ISA_BUS
    HardwareReadRegWord( pHardware,
                         (UCHAR)REG_SWITCH_CTRL_BANK,
                         (UCHAR)REG_CHIP_ID_OFFSET,
                         (PUSHORT)&RegData
                       );
#else
    HW_READ_WORD( pHardware, REG_CHIP_ID_OFFSET, &RegData );
#endif


    *pChipID        = RegData & SWITCH_CHIP_ID_MASK;
    *pDevRevisionID = RegData & SWITCH_REVISION_MASK;

}  /* HardwareReadChipID */


/*
    HardwareReset

    Description:
        This function resets the hardware.

    Parameters:
        PHARDWARE pHardware
            Pointer to hardware instance.

    Return (BOOLEAN):
        TRUE if successful; otherwise, FALSE.
*/

#ifdef KS_PCI_BUS
BOOLEAN HardwareReset_PCI
#else
BOOLEAN HardwareReset_ISA
#endif
(
    PHARDWARE pHardware )
{

    /* Write 1 to reset device */
#ifdef KS_ISA_BUS
    HardwareWriteRegWord( pHardware, REG_GLOBAL_CTRL_BANK,
        REG_GLOBAL_CTRL_OFFSET, GLOBAL_SOFTWARE_RESET );
#endif

#ifdef KS_PCI_BUS
    HW_WRITE_WORD( pHardware,
        REG_GLOBAL_CTRL_OFFSET, GLOBAL_SOFTWARE_RESET );
#endif

    /* Wait for device to reset */
    DelayMillisec( 10 );

    /* Write 0 to clear device reset */
#ifdef KS_ISA_BUS
    HardwareWriteRegWord( pHardware, REG_GLOBAL_CTRL_BANK,
        REG_GLOBAL_CTRL_OFFSET, 0 );
#endif

#ifdef KS_PCI_BUS
    HW_WRITE_WORD( pHardware,
        REG_GLOBAL_CTRL_OFFSET, 0 );
#endif

#ifdef DEBUG_COUNTER
    pHardware->m_nGood[ COUNT_GOOD_CMD_RESET ]+=1;
#endif
    return TRUE;
}  /* HardwareReset */


#ifdef KS_ISA_BUS
/*
    HardwareSetBurst

    Description:
        This function is to setup Burst mode with its burst length.
        Note: The burst length should be the same as Host's burst length.

    Parameters:
        PHARDWARE pHardware
            Pointer to hardware instance.

        UCHAR  wBurstLength
            burst length (0, 4, 8,16).

    Return (BOOLEAN):
        TRUE successful; otherwise, FALSE.
*/

BOOLEAN HardwareSetBurst (
    PHARDWARE pHardware,
    UCHAR     bBurstLength )
{
    USHORT     RegData;


    switch (bBurstLength)
    {
        case 0:
            RegData = BURST_LENGTH_0 ;
            break;
        case 4:
            RegData = BURST_LENGTH_4 ;
            break;
        case 8:
            RegData = BURST_LENGTH_8 ;
            break;
        case 16:
            RegData = BURST_LENGTH_16 ;
            break;
        default:
            return (FALSE);
    }

    HardwareWriteRegWord( pHardware, REG_BUS_BURST_BANK, REG_BUS_BURST_OFFSET,
                          RegData );
    return (TRUE);

}  /* HardwareSetBurst */

#endif /* #ifdef KS_ISA_BUS */


/*
    HardwareSetup

    Description:
        This routine setup the hardware for proper operation.

    Parameters:
        PHARDWARE pHardware
            Pointer to hardware instance.

    Return (None):
*/

#ifdef KS_PCI_BUS
void HardwareSetup_PCI
#else
void HardwareSetup_ISA
#endif
(
    PHARDWARE pHardware )
{
#if defined( DEF_KS8841 ) && ( defined( EARLY_TRANSMIT ) || defined( EARLY_RECEIVE ))
    USHORT RegData;
#endif

    /*
     * Initialize Tx\Rx control setting.
     */

    /* KS_PCI_BUS */

#ifdef KS_PCI_BUS

    /* Setup Transmit Control */

#ifdef DEBUG_HARDWARE_SETUP
    DBG_PRINT( "HardwareSetup_PCI(): Initialize Tx/Rx control setting"NEWLINE );
#endif

    pHardware->m_dwTransmitConfig = ( DMA_TX_CTRL_PAD_ENABLE | DMA_TX_CTRL_CRC_ENABLE |
                                     (PBL_DEFAULT << 24) | DMA_TX_CTRL_ENABLE );
#if FLOWCONTROL_DEFAULT
    pHardware->m_dwTransmitConfig |= DMA_TX_CTRL_FLOW_ENABLE;
#else
    pHardware->m_dwTransmitConfig &= ~DMA_TX_CTRL_FLOW_ENABLE;
#endif

#if TXCHECKSUM_DEFAULT
    /* Hardware cannot handle UDP packet in IP fragments. */
    pHardware->m_dwTransmitConfig |= (DMA_TX_CTRL_CSUM_TCP | DMA_TX_CTRL_CSUM_IP);
#else
    pHardware->m_dwTransmitConfig &= ~(DMA_TX_CTRL_CSUM_UDP | DMA_TX_CTRL_CSUM_TCP | DMA_TX_CTRL_CSUM_IP);
#endif /* TXCHECKSUM_DEFAULT */

#if 0
    pHardware->m_dwTransmitConfig |= DMA_TX_CTRL_LOOPBACK;
#endif

    /* Setup Receive Control */

    pHardware->m_dwReceiveConfig = ( DMA_RX_CTRL_BROADCAST | DMA_RX_CTRL_UNICAST |
                                    (PBL_DEFAULT << 24) | DMA_RX_CTRL_ENABLE );

#if FLOWCONTROL_DEFAULT
    pHardware->m_dwReceiveConfig |= DMA_RX_CTRL_FLOW_ENABLE;
#else
    pHardware->m_dwReceiveConfig &= ~DMA_RX_CTRL_FLOW_ENABLE;
#endif

#if RXCHECKSUM_DEFAULT
    /* Hardware cannot handle UDP packet in IP fragments. */
    pHardware->m_dwReceiveConfig |= (DMA_RX_CTRL_CSUM_TCP | DMA_RX_CTRL_CSUM_IP);
#else
    pHardware->m_dwReceiveConfig &= ~(DMA_RX_CTRL_CSUM_UDP | DMA_RX_CTRL_CSUM_TCP | DMA_RX_CTRL_CSUM_IP);
#endif
    pHardware->m_dwReceiveConfig |= DMA_RX_CTRL_MULTICAST;

    if ( pHardware->m_bAllMulticast )
        pHardware->m_dwReceiveConfig |= DMA_RX_CTRL_ALL_MULTICAST;
    if ( pHardware->m_bPromiscuous )
        pHardware->m_dwReceiveConfig |= DMA_RX_CTRL_PROMISCUOUS;

#if defined( CHECK_RCV_ERRORS ) || defined( RCV_HUGE_FRAME )
    pHardware->m_dwReceiveConfig |= DMA_RX_CTRL_ERROR;
#endif

#else /* #ifdef KS_ISA_BUS  */

    /* KS_ISA_BUS  */


    /* Setup Transmit Control */

    pHardware->m_wTransmitConfig = TX_CTRL_PAD_ENABLE | TX_CTRL_ENABLE;

#if 0
    pHardware->m_wTransmitConfig |= TX_CTRL_EPH_LOOPBACK;
#endif

    pHardware->m_wTransmitConfig |= ( TX_CTRL_CRC_ENABLE | TX_CTRL_FLOW_ENABLE );


    /* Setup Transmit Frame Data Pointer Auto-Increment */
    HardwareWriteRegWord( pHardware, REG_TX_ADDR_PTR_BANK,
        REG_TX_ADDR_PTR_OFFSET, ADDR_PTR_AUTO_INC | 0 );


  #if defined (EARLY_TRANSMIT) && defined(DEF_KS8841)

    /* Setup Early Transmit function */
    pHardware->m_wTransmitThreshold = EARLY_TX_MULTIPLE;

    HardwareReadRegWord( pHardware, REG_EARLY_TX_BANK, REG_EARLY_TX_OFFSET,
                        &RegData );
    RegData &= ~EARLY_TX_THRESHOLD;
    RegData |= pHardware->m_wTransmitThreshold / EARLY_TX_MULTIPLE;
    RegData |= EARLY_TX_ENABLE;

    HardwareWriteRegWord( pHardware, REG_EARLY_TX_BANK, REG_EARLY_TX_OFFSET,
                          RegData );

  #endif /* #ifdef EARLY_TRANSMIT */



    /* Setup Receive Control */

    pHardware->m_wReceiveConfig = RX_CTRL_STRIP_CRC | RX_CTRL_ENABLE;
    pHardware->m_wReceiveConfig |= ( RX_CTRL_UNICAST | RX_CTRL_BROADCAST | RX_CTRL_FLOW_ENABLE );
    pHardware->m_wReceiveConfig |= RX_CTRL_MULTICAST;

    if ( pHardware->m_bAllMulticast )
        pHardware->m_wReceiveConfig |= RX_CTRL_ALL_MULTICAST;
    if ( pHardware->m_bPromiscuous )
        pHardware->m_wReceiveConfig |= RX_CTRL_PROMISCUOUS;

    /* Setup Receive Frame Data Pointer Auto-Increment */
    HardwareWriteRegWord( pHardware, REG_RX_ADDR_PTR_BANK,
                          REG_RX_ADDR_PTR_OFFSET, ADDR_PTR_AUTO_INC | 0 );

    /* Setup Receive High Water Mark to 2KBytes to avoid loss packets (big packet size) under flow control */
    HardwareWriteRegWord( pHardware, REG_RX_WATERMARK_BANK,
                          REG_RX_WATERMARK_OFFSET, RX_HIGH_WATERMARK_2KB );

  #if defined (EARLY_RECEIVE) && defined(DEF_KS8841)

    /* Setup Early Receive function */
    pHardware->m_wReceiveThreshold = EARLY_RX_MULTIPLE;

    HardwareReadRegWord( pHardware, REG_EARLY_RX_BANK, REG_EARLY_RX_OFFSET,
                         &RegData );

    RegData &= ~EARLY_RX_THRESHOLD;
    RegData |= pHardware->m_wReceiveThreshold / EARLY_RX_MULTIPLE;
    RegData |= EARLY_RX_ENABLE;

    HardwareWriteRegWord( pHardware, REG_EARLY_RX_BANK, REG_EARLY_RX_OFFSET,
                          RegData );

  #endif /* #if defined ( EARLY_RECEIVE ) && defined( DEF_KS8841 )  */




#endif /* #ifdef KS_PCI_BUS */

    /*
     * Initialize Port control setting.
     */

    SwitchSetGlobalControl( pHardware );

    /* Enable WOL by detection of magic packet */
    HardwareEnableWolMagicPacket ( pHardware );
    HardwareClearWolPMEStatus ( pHardware );

}  /* HardwareSetup */


/*
    HardwareSwitchSetup

    Description:
        This routine setup the hardware Switch engine for default operation.

    Parameters:
        PHARDWARE pHardware
            Pointer to hardware instance.

    Return (None):
*/

void HardwareSwitchSetup
(
    PHARDWARE pHardware )
{
#ifdef DEF_KS8842
    UCHAR  bPort;
#endif

    /*
     * Initialize Port control setting.
     */

#ifdef DEBUG_HARDWARE_SETUP
    DBG_PRINT( "HardwareSetup(): calling SwitchSetLinkSpeed()"NEWLINE );
#endif
    SwitchSetLinkSpeed( pHardware );

#ifdef DEF_KS8842

#ifdef DEBUG_HARDWARE_SETUP
    DBG_PRINT( "HardwareSetup(): calling SwitchInitBroadcastStorm()"NEWLINE );
#endif
    /* Enable Switch Ports broacast storm protection at 10% percent rate */
    SwitchInitBroadcastStorm( pHardware );
    HardwareConfigBroadcastStorm( pHardware, BROADCAST_STORM_PROTECTION_RATE );
    for ( bPort = 0; bPort < SWITCH_PORT_NUM; bPort++ )
        SwitchEnableBroadcastStorm( pHardware, bPort );

#ifdef DEBUG_HARDWARE_SETUP
    DBG_PRINT( "HardwareSetup(): calling SwitchInitPriority()"NEWLINE );
#endif
    SwitchInitPriority( pHardware );

#ifdef DEBUG_HARDWARE_SETUP
    DBG_PRINT( "HardwareSetup(): calling SwitchInitMirror()"NEWLINE );
#endif
    SwitchInitMirror( pHardware );

#ifdef DEBUG_HARDWARE_SETUP
    DBG_PRINT( "HardwareSetup(): calling SwitchInitPriorityRate()"NEWLINE );
#endif
    SwitchInitPriorityRate( pHardware );

#ifdef DEBUG_HARDWARE_SETUP
    DBG_PRINT( "HardwareSetup(): calling SwitchInitVlan()"NEWLINE );
#endif
    SwitchInitVlan( pHardware );

#ifdef SOFTWARE_STP_SUPPORT
#ifdef DEBUG_HARDWARE_SETUP
    DBG_PRINT( "HardwareSetup(): calling HardwareInit_STP()"NEWLINE );
#endif
    HardwareInit_STP( pHardware );
#endif

    SwitchEnable( pHardware, TRUE );