ks_table.c

MICREL 网卡驱动 FOR CE 5.0

    PUSHORT   pwVID,
    PUCHAR    pbFID,
    PUCHAR    pbMember )
{
    ULONG dwData;

    ASSERT( pHardware->m_bAcquire );

#ifdef KS_ISA_BUS
#ifdef KS_PCI
    if ( !pHardware->m_fPCI )
#endif
    {
        SwitchReadTable_ISA( pHardware, TABLE_VLAN, wAddr, &dwData );
    }

#ifdef KS_PCI
    else
#endif
#endif

#ifdef KS_PCI
    {
        SwitchReadTable_PCI( pHardware, TABLE_VLAN, wAddr, &dwData );
    }
#endif
    if ( ( dwData & VLAN_TABLE_VALID ) )
    {
        *pwVID = ( USHORT )( dwData & VLAN_TABLE_VID );
        *pbFID = ( UCHAR )(( dwData & VLAN_TABLE_FID ) >>
            VLAN_TABLE_FID_SHIFT );
        *pbMember = ( UCHAR )(( dwData & VLAN_TABLE_MEMBERSHIP ) >>
            VLAN_TABLE_MEMBERSHIP_SHIFT );
        return TRUE;
    }
    return FALSE;
}  /* SwitchReadVlanTable */


/*
    SwitchWriteVlanTable

    Description:
        This routine writes an entry of the VLAN table of the switch.  It calls
        SwitchWriteTable() to write the data.

    Parameters:
        PHARDWARE pHardware
            Pointer to hardware instance.

        USHORT wAddr
            The address of the entry.

        USHORT wVID
            The VID value.

        UCHAR bFID
            The FID value.

        UCHAR bMember
            The port membership.

        BOOLEAN fValid
            The valid flag to indicate entry is valid.

    Return (None):
*/

void SwitchWriteVlanTable (
    PHARDWARE pHardware,
    USHORT    wAddr,
    USHORT    wVID,
    UCHAR     bFID,
    UCHAR     bMember,
    BOOLEAN   fValid )
{
    ULONG dwData;

    ASSERT( pHardware->m_bAcquire );

    dwData = wVID;
    dwData |= ( ULONG ) bFID << VLAN_TABLE_FID_SHIFT;
    dwData |= ( ULONG ) bMember << VLAN_TABLE_MEMBERSHIP_SHIFT;
    if ( fValid )
        dwData |= VLAN_TABLE_VALID;

#ifdef KS_ISA_BUS
#ifdef KS_PCI
    if ( !pHardware->m_fPCI )
#endif
    {
        /* v1.0.5 deleted.
        dwData = SwapBytes( dwData );
        */
        SwitchWriteTable_ISA( pHardware, TABLE_VLAN, wAddr, dwData );
    }

#ifdef KS_PCI
    else
#endif
#endif

#ifdef KS_PCI
    {
        SwitchWriteTable_PCI( pHardware, TABLE_VLAN, wAddr, dwData );
    }
#endif
}  /* SwitchWriteVlanTable */
#endif

/* -------------------------------------------------------------------------- */

#define MIB_COUNTER_PACKET_DROPPED_TX_0  0x100
#define MIB_COUNTER_PACKET_DROPPED_TX_1  0x101
#define MIB_COUNTER_PACKET_DROPPED_TX_2  0x102
#define MIB_COUNTER_PACKET_DROPPED_RX_0  0x103
#define MIB_COUNTER_PACKET_DROPPED_RX_1  0x104
#define MIB_COUNTER_PACKET_DROPPED_RX_2  0x105


/*
    PortReadMIBCounter

    Description:
        This routine reads a MIB counter of the port.
        Hardware interrupts are disabled to minimize corruption of read data.

    Parameters:
        PHARDWARE pHardware
            Pointer to hardware instance.

        UCHAR bPort
            The port index.

        USHORT wAddr
            The address of the counter.

        PULONGLONG pqData
            Buffer to store the counter.

    Return (None):
*/

#ifdef KS_PCI_BUS
void PortReadMIBCounter_PCI
#else
void PortReadMIBCounter_ISA
#endif
(
    PHARDWARE  pHardware,
    UCHAR      bPort,
    USHORT     wAddr,
    PULONGLONG pqData )
{
    ULONG      dwData;
    UCHAR      bAddr;
    UCHAR      bCtrl;
    USHORT     wCtrlAddr;

#ifdef KS_PCI_BUS
    ULONG InterruptMask;

#else
    USHORT InterruptMask;
#endif
    int   cnTimeOut;

    wAddr += PORT_COUNTER_NUM * bPort;
    bAddr = ( UCHAR ) wAddr;
    bCtrl = ( UCHAR )(( TABLE_MIB << TABLE_SEL_SHIFT ) | ( wAddr >> 8 ) |
        TABLE_READ );

    wCtrlAddr = bCtrl;
    wCtrlAddr = (wCtrlAddr << 8) | bAddr ;

    /* Save the current interrupt mask and block all interrupts. */
    InterruptMask = HardwareBlockInterrupt( pHardware );

#ifdef KS_ISA_BUS
    HardwareWriteRegWord( pHardware,
                                  (UCHAR)REG_IND_ACC_CTRL_BANK,
                                  (UCHAR)REG_IACR_OFFSET,
                                  wCtrlAddr
                                );
#else
    HW_WRITE_WORD( pHardware, REG_IACR_OFFSET, wCtrlAddr );
#endif

    for ( cnTimeOut = 100; cnTimeOut > 0; cnTimeOut-- )
    {

#ifdef KS_ISA_BUS
        HardwareSelectBank( pHardware, REG_IND_ACC_CTRL_BANK );
        HardwareReadRegDWord( pHardware,
                                 (UCHAR)REG_IND_ACC_CTRL_BANK,
                                 (UCHAR)REG_ACC_DATA_0_OFFSET,
                                 (PULONG)&dwData
                               );
#else
        HW_READ_DWORD( pHardware, REG_ACC_DATA_0_OFFSET, &dwData );
#endif

        if ( ( dwData & MIB_COUNTER_VALID ) )
        {
            if ( ( dwData & MIB_COUNTER_OVERFLOW ) )
            {
                *pqData += MIB_COUNTER_VALUE + 1;
            }
            *pqData += dwData & MIB_COUNTER_VALUE;
            break;
        }
    }

    /* Restore the interrupt mask. */
    HardwareSetInterrupt( pHardware, InterruptMask );
}  /* PortReadMIBCounter */


/*
    PortReadMIBPacket

    Description:
        This routine reads the dropped packet counts of the port.
        Hardware interrupts are disabled to minimize corruption of read data.

    Parameters:
        PHARDWARE pHardware
            Pointer to hardware instance.

        UCHAR bPort
            The port index.

        PULONGLONG pqData
            Buffer to store the receive and transmit dropped packet counts.

    Return (None):
*/

#ifdef KS_PCI_BUS
void PortReadMIBPacket_PCI
#else
void PortReadMIBPacket_ISA
#endif
(
    PHARDWARE  pHardware,
    UCHAR      bPort,
    PULONG     pdwCurrent,
    PULONGLONG pqData )
{
    ULONG     dwCurrent;
    ULONG     dwData = 0;
    USHORT    wAddr;
    UCHAR     bAddr;
    UCHAR     bCtrl;
    USHORT    wCtrlAddr;

#ifdef KS_PCI_BUS
    ULONG     InterruptMask;

#else
    USHORT    InterruptMask;
#endif


    wAddr = MIB_COUNTER_PACKET_DROPPED_RX_0 + bPort;
    bAddr = ( UCHAR ) wAddr;
    bCtrl = ( UCHAR )(( TABLE_MIB << TABLE_SEL_SHIFT ) | ( wAddr >> 8 ) |
        TABLE_READ );

    wCtrlAddr = bCtrl;
    wCtrlAddr = (wCtrlAddr << 8) | bAddr ;

    /* Save the current interrupt mask and block all interrupts. */
    InterruptMask = HardwareBlockInterrupt( pHardware );

#ifdef KS_ISA_BUS
    HardwareWriteRegWord( pHardware,
                          (UCHAR)REG_IND_ACC_CTRL_BANK,
                          (UCHAR)REG_IACR_OFFSET,
                          wCtrlAddr
                        );
    HardwareReadRegDWord( pHardware,
                          (UCHAR)REG_IND_ACC_CTRL_BANK,
                          (UCHAR)REG_ACC_DATA_0_OFFSET,
                          &dwData
                        );
#else
    HW_WRITE_WORD( pHardware, REG_IACR_OFFSET, wCtrlAddr );
    HW_READ_DWORD( pHardware, REG_ACC_DATA_0_OFFSET, &dwData );

#endif

    dwData &= MIB_COUNTER_PACKET_DROPPED;
    dwCurrent = *pdwCurrent;
    if ( dwData != dwCurrent )
    {
        if ( dwData < dwCurrent )
        {
            dwData += MIB_COUNTER_PACKET_DROPPED + 1;
        }
        dwData -= dwCurrent;
        *pqData += dwData;
        *pdwCurrent = dwCurrent;
    }
    ++pdwCurrent;
    ++pqData;
    wAddr = MIB_COUNTER_PACKET_DROPPED_TX_0 + bPort;
    bAddr = ( UCHAR ) wAddr;

    wCtrlAddr = bCtrl;
    wCtrlAddr = (wCtrlAddr << 8) | bAddr ;

#ifdef KS_ISA_BUS
    HardwareSelectBank( pHardware, REG_IND_ACC_CTRL_BANK );

    HardwareWriteRegWord( pHardware,
                          (UCHAR)REG_IND_ACC_CTRL_BANK,
                          (UCHAR)REG_IACR_OFFSET,
                          wCtrlAddr
                        );
    HardwareReadRegDWord( pHardware,
                          (UCHAR)REG_IND_ACC_CTRL_BANK,
                          (UCHAR)REG_ACC_DATA_0_OFFSET,
                          &dwData
                        );
#else
    HW_WRITE_WORD( pHardware, REG_IACR_OFFSET, wCtrlAddr );
    HW_READ_DWORD( pHardware, REG_ACC_DATA_0_OFFSET, &dwData );
#endif

    dwData &= MIB_COUNTER_PACKET_DROPPED;
    dwCurrent = ( ULONG )( *pqData & MIB_COUNTER_PACKET_DROPPED );
    if ( dwData != dwCurrent )
    {
        if ( dwData < dwCurrent )
        {
            dwData += MIB_COUNTER_PACKET_DROPPED + 1;
        }
        dwData -= dwCurrent;
        *pqData += dwData;
    }

    /* Restore the interrupt mask. */
    HardwareSetInterrupt( pHardware, InterruptMask );
}  /* PortReadMIBPacket */


#if defined( KS_ISA_BUS )  ||  !defined( KS_ISA )

/*
    PortReadCounters

    Description:
        This routine is used to read the counters of the port periodically to
        avoid counter overflow.  The hardware should be acquired first before
        calling this routine.

    Parameters:
        PHARDWARE pHardware
            Pointer to hardware instance.

        UCHAR bPort
            The port index.

    Return (int):
        non-zero when not all counters not read.
*/

int PortReadCounters (
    PHARDWARE pHardware,
    UCHAR     bPort )
{
    PPORT_CONFIG pPort = &pHardware->m_Port[ bPort ];

#ifdef KS_PCI_BUS
    ULONG        IntEnable;
    ULONG        IntMask = pHardware->m_ulInterruptMask;

#else
    USHORT       IntEnable;
    USHORT       IntMask = pHardware->m_wInterruptMask;
#endif

    ASSERT( pHardware->m_bAcquire );

    do
    {
        PortReadMIBCounter( pHardware, bPort, pPort->bCurrentCounter,
            &pPort->cnCounter[ pPort->bCurrentCounter ]);
        ++pPort->bCurrentCounter;

        /* Do table read in stages to allow interrupt processing. */
        HardwareReadInterrupt( pHardware, &IntEnable );
        if ( (( IntMask & IntEnable ) & INT_RX ) )
            return( pPort->bCurrentCounter );

#if (0)
        switch ( pPort->bCurrentCounter )
        {
            case MIB_COUNTER_RX_UNDERSIZE:
                return( pPort->bCurrentCounter );
            case MIB_COUNTER_RX_SYMBOL_ERR:
                return( pPort->bCurrentCounter );
            case MIB_COUNTER_RX_BROADCAST:
                return( pPort->bCurrentCounter );
            case MIB_COUNTER_RX_OCTET_64:
                return( pPort->bCurrentCounter );
            case MIB_COUNTER_TX_LO_PRIORITY:
                return( pPort->bCurrentCounter );
            case MIB_COUNTER_TX_BROADCAST:
                return( pPort->bCurrentCounter );
            case MIB_COUNTER_TX_TOTAL_COLLISION:
                return( pPort->bCurrentCounter );
        }
#endif
    } while ( pPort->bCurrentCounter < PORT_COUNTER_NUM );
    if ( bPort < HOST_PORT )
        PortReadMIBPacket( pHardware, bPort, pPort->cnDropped,
            &pPort->cnCounter[ pPort->bCurrentCounter ]);
    pPort->bCurrentCounter = 0;
    return 0;
}  /* PortReadCounters */


/*
    PortInitCounters

    Description:
        This routine is used to initialize all counters to zero if the hardware
        cannot do it after reset.

    Parameters:
        PHARDWARE pHardware
            Pointer to hardware instance.

        UCHAR bPort
            The port index.

    Return (None):
*/

void PortInitCounters (
    PHARDWARE pHardware,
    UCHAR     bPort )
{
    PPORT_CONFIG pPort = &pHardware->m_Port[ bPort ];


    ASSERT( pHardware->m_bAcquire );

    pPort->bCurrentCounter = 0;
    do
    {
        PortReadMIBCounter( pHardware, bPort, pPort->bCurrentCounter,
            &pPort->cnCounter[ pPort->bCurrentCounter ]);
        ++pPort->bCurrentCounter;
    } while ( pPort->bCurrentCounter < PORT_COUNTER_NUM );

    PortReadMIBPacket( pHardware, bPort, pPort->cnDropped,
        &pPort->cnCounter[ pPort->bCurrentCounter ]);
    memset(( void* ) pPort->cnCounter, 0,
        sizeof( ULONGLONG ) * TOTAL_PORT_COUNTER_NUM );
    pPort->bCurrentCounter = 0;
}  /* PortInitCounters */


#endif