📄 ks_table.c
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/* ---------------------------------------------------------------------------
Copyright (c) 2004-2006 Micrel, Inc. All rights reserved.
---------------------------------------------------------------------------
ks_table.c - KS884X switch table functions.
Author Date Version Description
PCD 06/07/06 1.0.5 Don't do byte swap in SwitchWriteVlanTable().
THa 02/23/06 Removed KS884X_HW conditional.
PCD 05/25/05 0.1.4 Modify the way to read\write table registers in KS_ISA_BUS interface.
THa 09/29/04 Updated for PCI version.
THa 02/13/04 Created file.
---------------------------------------------------------------------------
*/
#include "target.h"
#include "hardware.h"
/* -------------------------------------------------------------------------- */
#define TABLE_READ 0x10
#define TABLE_SEL_SHIFT 2
/* -------------------------------------------------------------------------- */
/*
SwitchReadTable
Description:
This routine reads 4 bytes of data from the table of the switch.
Hardware interrupts are disabled to minimize corruption of read data.
Parameters:
PHARDWARE pHardware
Pointer to hardware instance.
int nTable
The table selector.
USHORT wAddr
The address of the table entry.
PULONG pdwData
Buffer to store the read data.
Return (None):
*/
#ifdef KS_PCI_BUS
void SwitchReadTable_PCI
#else
void SwitchReadTable_ISA
#endif
(
PHARDWARE pHardware,
int nTable,
USHORT wAddr,
PULONG pdwData )
{
UCHAR bAddr;
UCHAR bCtrl;
USHORT wCtrlAddr;
#ifdef KS_PCI_BUS
ULONG InterruptMask;
#else
USHORT InterruptMask;
#endif
bAddr = ( UCHAR ) wAddr;
bCtrl = ( UCHAR )(( nTable << TABLE_SEL_SHIFT ) | ( wAddr >> 8 ) |
TABLE_READ );
wCtrlAddr = bCtrl;
wCtrlAddr = (wCtrlAddr << 8) | bAddr ;
/* Save the current interrupt mask and block all interrupts. */
InterruptMask = HardwareBlockInterrupt( pHardware );
#ifdef KS_ISA_BUS
HardwareWriteRegWord( pHardware,
(UCHAR)REG_IND_ACC_CTRL_BANK,
(UCHAR)REG_IACR_OFFSET,
(USHORT)wCtrlAddr
);
HardwareReadRegDWord( pHardware,
(UCHAR)REG_IND_ACC_CTRL_BANK,
(UCHAR)REG_ACC_DATA_0_OFFSET,
(PULONG)pdwData
);
#else
HW_WRITE_WORD( pHardware, REG_IACR_OFFSET, wCtrlAddr );
HW_READ_DWORD( pHardware, REG_ACC_DATA_0_OFFSET, pdwData );
#endif
/* Restore the interrupt mask. */
HardwareSetInterrupt( pHardware, InterruptMask );
} /* SwitchReadTable */
/*
SwitchWriteTable
Description:
This routine writes 4 bytes of data to the table of the switch.
Hardware interrupts are disabled to minimize corruption of written data.
Parameters:
PHARDWARE pHardware
Pointer to hardware instance.
int nTable
The table selector.
USHORT wAddr
The address of the table entry.
ULONG dwData
Data to be written.
Return (None):
*/
#ifdef KS_PCI_BUS
void SwitchWriteTable_PCI
#else
void SwitchWriteTable_ISA
#endif
(
PHARDWARE pHardware,
int nTable,
USHORT wAddr,
ULONG dwData )
{
UCHAR bAddr;
UCHAR bCtrl;
USHORT wCtrlAddr;
#ifdef KS_PCI_BUS
ULONG InterruptMask;
#else
USHORT InterruptMask;
#endif
bAddr = ( UCHAR ) wAddr;
bCtrl = ( UCHAR )(( nTable << TABLE_SEL_SHIFT ) | ( wAddr >> 8 ));
wCtrlAddr = bCtrl;
wCtrlAddr = (wCtrlAddr << 8) | bAddr ;
/* Save the current interrupt mask and block all interrupts. */
InterruptMask = HardwareBlockInterrupt( pHardware );
#ifdef KS_ISA_BUS
HardwareWriteRegDWord( pHardware,
(UCHAR)REG_IND_ACC_CTRL_BANK,
(UCHAR)REG_ACC_DATA_0_OFFSET,
dwData
);
HardwareWriteRegWord( pHardware,
(UCHAR)REG_IND_ACC_CTRL_BANK,
(UCHAR)REG_IACR_OFFSET,
wCtrlAddr
);
#else
HW_WRITE_DWORD( pHardware, REG_ACC_DATA_0_OFFSET, dwData );
HW_WRITE_WORD( pHardware, REG_IACR_OFFSET, wCtrlAddr );
#endif
/* Restore the interrupt mask. */
HardwareSetInterrupt( pHardware, InterruptMask );
} /* SwitchWriteTable */
/*
SwitchReadTableQword
Description:
This routine reads 8 bytes of data from the table of the switch.
Hardware interrupts are disabled to minimize corruption of read data.
Parameters:
PHARDWARE pHardware
Pointer to hardware instance.
int nTable
The table selector.
USHORT wAddr
The address of the table entry.
PULONG pdwDataHi
Buffer to store the high part of read data (bit63 ~ bit32).
PULONG pdwDataLo
Buffer to store the low part of read data (bit31 ~ bit0).
Return (None):
*/
#ifdef KS_PCI_BUS
void SwitchReadTableQword_PCI
#else
void SwitchReadTableQword_ISA
#endif
(
PHARDWARE pHardware,
int nTable,
USHORT wAddr,
PULONG pdwDataHi,
PULONG pdwDataLo )
{
UCHAR bAddr;
UCHAR bCtrl;
USHORT wCtrlAddr;
#ifdef KS_PCI_BUS
ULONG InterruptMask;
#else
USHORT InterruptMask;
#endif
bAddr = ( UCHAR ) wAddr;
bCtrl = ( UCHAR )(( nTable << TABLE_SEL_SHIFT ) | ( wAddr >> 8 ) |
TABLE_READ );
wCtrlAddr = bCtrl;
wCtrlAddr = (wCtrlAddr << 8) | bAddr ;
/* Save the current interrupt mask and block all interrupts. */
InterruptMask = HardwareBlockInterrupt( pHardware );
#ifdef KS_ISA_BUS
HardwareWriteRegWord( pHardware,
(UCHAR)REG_IND_ACC_CTRL_BANK,
(UCHAR)REG_IACR_OFFSET,
(USHORT)wCtrlAddr
);
HardwareReadRegDWord( pHardware,
(UCHAR)REG_IND_ACC_CTRL_BANK,
(UCHAR)REG_ACC_DATA_4_OFFSET,
pdwDataHi
);
HardwareReadRegDWord( pHardware,
(UCHAR)REG_IND_ACC_CTRL_BANK,
(UCHAR)REG_ACC_DATA_0_OFFSET,
pdwDataLo
);
#else
HW_WRITE_WORD( pHardware, REG_IACR_OFFSET, wCtrlAddr );
HW_READ_DWORD( pHardware, REG_ACC_DATA_4_OFFSET, pdwDataHi );
HW_READ_DWORD( pHardware, REG_ACC_DATA_0_OFFSET, pdwDataLo );
#endif
/* Restore the interrupt mask. */
HardwareSetInterrupt( pHardware, InterruptMask );
} /* SwitchReadTableQword */
/*
SwitchWriteTableQword
Description:
This routine writes 8 bytes of data to the table of the switch.
Hardware interrupts are disabled to minimize corruption of written data.
Parameters:
PHARDWARE pHardware
Pointer to hardware instance.
int nTable
The table selector.
USHORT wAddr
The address of the table entry.
ULONG dwDataHi
The high part of data to be written (bit63 ~ bit32).
ULONG dwDataLo
The low part of data to be written (bit31 ~ bit0).
Return (None):
*/
#ifdef KS_PCI_BUS
void SwitchWriteTableQword_PCI
#else
void SwitchWriteTableQword_ISA
#endif
(
PHARDWARE pHardware,
int nTable,
USHORT wAddr,
ULONG dwDataHi,
ULONG dwDataLo )
{
UCHAR bAddr;
UCHAR bCtrl;
USHORT wCtrlAddr;
#ifdef KS_PCI_BUS
ULONG InterruptMask;
#else
USHORT InterruptMask;
#endif
bAddr = ( UCHAR ) wAddr;
bCtrl = ( UCHAR )(( nTable << TABLE_SEL_SHIFT ) | ( wAddr >> 8 ));
wCtrlAddr = bCtrl;
wCtrlAddr = (wCtrlAddr << 8) | bAddr ;
/* Save the current interrupt mask and block all interrupts. */
InterruptMask = HardwareBlockInterrupt( pHardware );
#ifdef KS_ISA_BUS
HardwareWriteRegDWord( pHardware,
(UCHAR)REG_IND_ACC_CTRL_BANK,
(UCHAR)REG_ACC_DATA_4_OFFSET,
dwDataHi
);
HardwareWriteRegDWord( pHardware,
(UCHAR)REG_IND_ACC_CTRL_BANK,
(UCHAR)REG_ACC_DATA_0_OFFSET,
dwDataLo
);
HardwareWriteRegWord( pHardware,
(UCHAR)REG_IND_ACC_CTRL_BANK,
(UCHAR)REG_IACR_OFFSET,
wCtrlAddr
);
#else
HW_WRITE_DWORD( pHardware, REG_ACC_DATA_4_OFFSET, dwDataHi );
HW_WRITE_DWORD( pHardware, REG_ACC_DATA_0_OFFSET, dwDataLo );
HW_WRITE_WORD( pHardware, REG_IACR_OFFSET, wCtrlAddr );
#endif
/* Restore the interrupt mask. */
HardwareSetInterrupt( pHardware, InterruptMask );
} /* SwitchWriteTableQword */
/*
SwitchReadTableAllword
Description:
This routine reads 10 bytes of data from the table of the switch.
Hardware interrupts are disabled to minimize corruption of read data.
Parameters:
PHARDWARE pHardware
Pointer to hardware instance.
int nTable
The table selector.
USHORT wAddr
The address of the table entry.
USHORT pwDataHi
Buffer to store the highest part of read data (bit79 ~ bit64).
PULONG pdwDataHi
Buffer to store the high part of read data (bit63 ~ bit32).
PULONG pdwDataLo
Buffer to store the low part of read data (bit31 ~ bit0).
Return (None):
*/
#ifdef KS_PCI_BUS
void SwitchReadTableAllword_PCI
#else
void SwitchReadTableAllword_ISA
#endif
(
PHARDWARE pHardware,
int nTable,
USHORT wAddr,
PUSHORT pwDataHi,
PULONG pdwDataHi,
PULONG pdwDataLo )
{
UCHAR bAddr;
UCHAR bCtrl;
USHORT wCtrlAddr;
#ifdef KS_PCI_BUS
ULONG InterruptMask;
#else
USHORT InterruptMask;
#endif
bAddr = ( UCHAR ) wAddr;
bCtrl = ( UCHAR )(( nTable << TABLE_SEL_SHIFT ) | ( wAddr >> 8 ) |
TABLE_READ );
wCtrlAddr = bCtrl;
wCtrlAddr = (wCtrlAddr << 8) | bAddr ;
/* Save the current interrupt mask and block all interrupts. */
InterruptMask = HardwareBlockInterrupt( pHardware );
#ifdef KS_ISA_BUS
HardwareWriteRegWord( pHardware,
(UCHAR)REG_IND_ACC_CTRL_BANK,
(UCHAR)REG_IACR_OFFSET,
wCtrlAddr
);
HardwareReadRegWord( pHardware,
(UCHAR)REG_IND_ACC_CTRL_BANK,
(UCHAR)REG_ACC_DATA_8_OFFSET,
pwDataHi
);
HardwareReadRegDWord( pHardware,
(UCHAR)REG_IND_ACC_CTRL_BANK,
(UCHAR)REG_ACC_DATA_4_OFFSET,
pdwDataHi
);
HardwareReadRegDWord( pHardware,
(UCHAR)REG_IND_ACC_CTRL_BANK,
(UCHAR)REG_ACC_DATA_0_OFFSET,
pdwDataLo
);
#else
HW_WRITE_WORD( pHardware, REG_IACR_OFFSET, wCtrlAddr );
HW_READ_WORD ( pHardware, REG_ACC_DATA_8_OFFSET, pwDataHi );
HW_READ_DWORD( pHardware, REG_ACC_DATA_4_OFFSET, pdwDataHi );
HW_READ_DWORD( pHardware, REG_ACC_DATA_0_OFFSET, pdwDataLo );
#endif
/* Restore the interrupt mask. */
HardwareSetInterrupt( pHardware, InterruptMask );
} /* SwitchReadTableAllword */
/* -------------------------------------------------------------------------- */
/*
#define STATIC_MAC_TABLE_ADDR 00-0000FFFF-FFFFFFFF
#define STATIC_MAC_TABLE_FWD_PORTS 00-00070000-00000000
#define STATIC_MAC_TABLE_VALID 00-00080000-00000000
#define STATIC_MAC_TABLE_OVERRIDE 00-00100000-00000000
#define STATIC_MAC_TABLE_USE_FID 00-00200000-00000000
#define STATIC_MAC_TABLE_FID 00-03C00000-00000000
*/
#define STATIC_MAC_TABLE_ADDR 0x0000FFFF
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