top_lc2.qsf

this a pack include source code for quartus 2. It is an implementation of the LC2. The LC-2 compu

# Copyright (C) 1991-2004 Altera Corporation
# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
# support information,  device programming or simulation file,  and any other
# associated  documentation or information  provided by  Altera  or a partner
# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
# other  use  of such  megafunction  design,  netlist,  support  information,
# device programming or simulation file,  or any other  related documentation
# or information  is prohibited  for  any  other purpose,  including, but not
# limited to  modification,  reverse engineering,  de-compiling, or use  with
# any other  silicon devices,  unless such use is  explicitly  licensed under
# a separate agreement with  Altera  or a megafunction partner.  Title to the
# intellectual property,  including patents,  copyrights,  trademarks,  trade
# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
# support  information,  device programming or simulation file,  or any other
# related documentation or information provided by  Altera  or a megafunction
# partner, remains with Altera, the megafunction partner, or their respective
# licensors. No other licenses, including any licenses needed under any third
# party's intellectual property, are provided herein.


# The default values for assignments are stored in the file
#		top_lc2_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 4.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:20:10  DECEMBER 10, 2004"
set_global_assignment -name LAST_QUARTUS_VERSION 4.2
set_global_assignment -name VHDL_FILE CHAR_ROM.VHD
set_global_assignment -name VECTOR_WAVEFORM_FILE top_lc2.vwf

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_62 -to PB1
set_location_assignment PIN_23 -to PB2
set_location_assignment PIN_227 -to Horiz_Sync
set_location_assignment PIN_226 -to Vert_Sync
set_location_assignment PIN_170 -to Blue
set_location_assignment PIN_122 -to Green
set_location_assignment PIN_228 -to Red
set_location_assignment PIN_29 -to clock_48Mhz
set_location_assignment PIN_58 -to SWITCH

# Timing Assignments
# ==================
set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS OFF

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL CUSTOM
set_global_assignment -name VHDL_INPUT_VERSION VHDL87
set_global_assignment -name FAMILY Cyclone
set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name TOP_LEVEL_ENTITY top_lc2
set_instance_assignment -name VHDL_INPUT_LIBRARY "c:\\booksoft\\chap5" -to "c:\\booksoft\\chap5"

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP1C6Q240C8
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name MAX7000B_VCCIO_IOBANK2 3.3V
set_global_assignment -name MAX7000B_VCCIO_IOBANK1 3.3V
set_instance_assignment -name IO_STANDARD LVTTL -to PB2
set_instance_assignment -name IO_STANDARD LVTTL -to PB1
set_instance_assignment -name IO_STANDARD LVTTL -to Green
set_instance_assignment -name IO_STANDARD LVTTL -to Blue
set_instance_assignment -name IO_STANDARD LVTTL -to Vert_Sync
set_instance_assignment -name IO_STANDARD LVTTL -to Horiz_Sync
set_instance_assignment -name IO_STANDARD LVTTL -to Red
set_instance_assignment -name IO_STANDARD LVTTL -to clock_48Mhz
set_instance_assignment -name IO_STANDARD LVTTL -to SWITCH

# Timing Analysis Assignments
# ===========================
set_global_assignment -name EXCLUDE_TPD_PATHS_LESS_THAN 0.0NS

# Assembler Assignments
# =====================
set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF

# Simulator Assignments
# =====================
set_global_assignment -name START_TIME 0.0ns
set_global_assignment -name SETUP_HOLD_DETECTION ON
set_global_assignment -name GLITCH_INTERVAL "0.0 "
set_global_assignment -name END_TIME "1.0 "

# LogicLock Region Assignments
# ============================
set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT off

# ---------------------------------------------
# start EDA_TOOL_SETTINGS(eda_design_synthesis)

	# Analysis & Synthesis Assignments
	# ================================
	set_global_assignment -name EDA_INPUT_DATA_FORMAT VHDL -section_id eda_design_synthesis

# end EDA_TOOL_SETTINGS(eda_design_synthesis)
# -------------------------------------------

# ---------------------
# start ENTITY(top_lc2)


	# ---------------------------------------------
	# start EDA_TOOL_SETTINGS(eda_design_synthesis)

		# Analysis & Synthesis Assignments
		# ================================
		set_instance_assignment -name EDA_VHDL_LIBRARY "c:\\booksoft\\chap5" -to "c:\\booksoft\\chap5" -section_id eda_design_synthesis

	# end EDA_TOOL_SETTINGS(eda_design_synthesis)
	# -------------------------------------------

# end ENTITY(top_lc2)
# -------------------