📄 dm642init.asm
字号:
;* SETUP CODE
;*
;* MVK 0x1,B0
;* ZERO A4
;*
;* SINGLE SCHEDULED ITERATION
;*
;* C47:
;* 0 MVKL .S1 0x1848204,A3 ; |351|
;* 1 MVKH .S1 0x1848204,A3 ; |351|
;* 2 [ B0] LDW .D1T1 *A3,A4 ; |351| ^
;* 3 NOP 4
;* 7 AND .D1 1,A4,A0 ; |351| ^
;* 8 [ A0] ZERO .D2 B0 ; ^
;* 9 [ B0] B .S2 C47 ; |351|
;* 10 NOP 5
;* ; BRANCH OCCURS ; |351|
;*----------------------------------------------------------------------------*
L5: ; PIPED LOOP PROLOG
;** --------------------------------------------------------------------------*
L6: ; PIPED LOOP KERNEL
[ A0] ZERO .D2 B0 ; <0,8> ^
|| MVKH .S1 0x1848204,A3 ; |351| <1,1>
[ B0] BNOP .S2 L6,4 ; |351| <0,9>
|| [ B0] LDW .D1T1 *A3,A4 ; |351| <1,2> ^
AND .D1 1,A4,A0 ; |351| <1,7> ^
|| MVKL .S1 0x1848204,A3 ; |351| <2,0>
;** --------------------------------------------------------------------------*
L7: ; PIPED LOOP EPILOG
;** --------------------------------------------------------------------------*
MVKL .S2 _EVMDM642_init,B4 ; |46|
MVKH .S2 _EVMDM642_init,B4 ; |46|
;** --------------------------------------------------------------------------*
L8:
CALL .S2 B4 ; |46|
ADDKPC .S2 RL0,B3,4 ; |46|
RL0: ; CALL OCCURS ; |46|
MVKL .S1 _EVMDM642_LED_init,A3 ; |47|
MVKH .S1 _EVMDM642_LED_init,A3 ; |47|
NOP 1
CALL .S2X A3 ; |47|
ADDKPC .S2 RL1,B3,4 ; |47|
RL1: ; CALL OCCURS ; |47|
MVKL .S2 _EVMDM642_EEPROM_read,B5 ; |50|
MVKH .S2 _EVMDM642_EEPROM_read,B5 ; |50|
CALL .S2 B5 ; |50|
MVKL .S1 _bMacAddr,A10 ; |50|
MVKH .S1 _bMacAddr,A10 ; |50|
MVK .S1 0x7f00,A4 ; |50|
MVK .D1 0x8,A6 ; |50|
MV .D2X A10,B4 ; |50|
|| ADDKPC .S2 RL2,B3,0 ; |50|
RL2: ; CALL OCCURS ; |50|
LDBU .D1T1 *A10,A3 ; |51|
NOP 3
MVK .S2 255,B4 ; |51|
CMPEQ .L2X A3,B4,B0 ; |51|
[!B0] B .S1 L10 ; |51|
MVK .S1 255,A3 ; |51|
|| MVK .S2 0xff,B4 ; |51|
|| [ B0] LDBU .D1T1 *+A10(1),A4 ; |51|
[!B0] MVKL .S1 _bMacAddr,A3 ; |64|
[!B0] MVKH .S1 _bMacAddr,A3 ; |64|
[!B0] LDBU .D1T1 *+A3(5),A5 ; |64|
[!B0] MVKL .S1 __remi,A3 ; |64|
|| [!B0] LDBU .D1T1 *+A3(7),A4 ; |64|
; BRANCH OCCURS ; |51|
;** --------------------------------------------------------------------------*
CMPEQ .L1 A4,A3,A0 ; |51|
[!A0] BNOP .S1 L10,1 ; |51|
[ A0] LDBU .D1T1 *+A10(2),A4 ; |51|
|| [!A0] MVKL .S1 _bMacAddr,A3 ; |64|
[!A0] MVKH .S1 _bMacAddr,A3 ; |64|
[!A0] LDBU .D1T1 *+A3(5),A5 ; |64|
[!A0] MVKL .S1 __remi,A3 ; |64|
|| [!A0] LDBU .D1T1 *+A3(7),A4 ; |64|
; BRANCH OCCURS ; |51|
;** --------------------------------------------------------------------------*
NOP 1
CMPEQ .L1 A4,A3,A0 ; |51|
[!A0] BNOP .S1 L10,1 ; |51|
[!A0] MVKL .S1 _bMacAddr,A3 ; |64|
|| [ A0] LDBU .D1T1 *+A10(3),A4 ; |51|
[!A0] MVKH .S1 _bMacAddr,A3 ; |64|
[!A0] LDBU .D1T1 *+A3(5),A5 ; |64|
[!A0] MVKL .S1 __remi,A3 ; |64|
|| [!A0] LDBU .D1T1 *+A3(7),A4 ; |64|
; BRANCH OCCURS ; |51|
;** --------------------------------------------------------------------------*
NOP 1
CMPEQ .L1 A4,A3,A0 ; |51|
[!A0] BNOP .S1 L10,1 ; |51|
[!A0] MVKL .S1 _bMacAddr,A3 ; |64|
|| [ A0] LDBU .D1T1 *+A10(4),A4 ; |51|
[!A0] MVKH .S1 _bMacAddr,A3 ; |64|
[!A0] LDBU .D1T1 *+A3(5),A5 ; |64|
[!A0] MVKL .S1 __remi,A3 ; |64|
|| [!A0] LDBU .D1T1 *+A3(7),A4 ; |64|
; BRANCH OCCURS ; |51|
;** --------------------------------------------------------------------------*
NOP 1
CMPEQ .L1 A4,A3,A0 ; |51|
[!A0] BNOP .S1 L10,1 ; |51|
[!A0] MVKL .S1 _bMacAddr,A3 ; |64|
|| [ A0] LDBU .D1T1 *+A10(5),A4 ; |51|
[!A0] MVKH .S1 _bMacAddr,A3 ; |64|
[!A0] LDBU .D1T1 *+A3(5),A5 ; |64|
[!A0] MVKL .S1 __remi,A3 ; |64|
|| [!A0] LDBU .D1T1 *+A3(7),A4 ; |64|
; BRANCH OCCURS ; |51|
;** --------------------------------------------------------------------------*
NOP 1
CMPEQ .L1 A4,A3,A0 ; |51|
[!A0] BNOP .S1 L10,1 ; |51|
[!A0] MVKL .S1 _bMacAddr,A3 ; |64|
|| [ A0] LDBU .D1T1 *+A10(6),A4 ; |51|
[!A0] MVKH .S1 _bMacAddr,A3 ; |64|
[!A0] LDBU .D1T1 *+A3(5),A5 ; |64|
[!A0] MVKL .S1 __remi,A3 ; |64|
|| [!A0] LDBU .D1T1 *+A3(7),A4 ; |64|
; BRANCH OCCURS ; |51|
;** --------------------------------------------------------------------------*
NOP 1
CMPEQ .L1 A4,A3,A0 ; |51|
[!A0] BNOP .S1 L9,1 ; |51|
[ A0] LDBU .D1T1 *+A10(7),A6 ; |51|
|| MVK .S1 255,A4 ; |51|
[!A0] MVKL .S1 _bMacAddr,A3 ; |64|
[!A0] MVKH .S1 _bMacAddr,A3 ; |64|
[!A0] LDBU .D1T1 *+A3(5),A5 ; |64|
; BRANCH OCCURS ; |51|
;** --------------------------------------------------------------------------*
MVKL .S2 0x1410444,B7 ; |56|
CMPEQ .L1 A6,A4,A0 ; |51|
[ A0] B .S1 L11 ; |51|
MVKL .S2 _LocalIPAddr,B6 ; |183|
MVKL .S2 SL7+0,B5 ; |186|
|| MVKL .S1 0x141015a,A5 ; |56|
MVKH .S2 0x1410444,B7 ; |56|
|| MVKL .S1 _bMacAddr,A3 ; |56|
MVKH .S2 _LocalIPAddr,B6 ; |183|
|| MVKH .S1 0x141015a,A5 ; |56|
MV .D1X B7,A4 ; |56|
|| MVKH .S2 SL7+0,B5 ; |186|
|| MVKH .S1 _bMacAddr,A3 ; |56|
; BRANCH OCCURS ; |51|
;** --------------------------------------------------------------------------*
MVKL .S1 _bMacAddr,A3 ; |64|
MVKH .S1 _bMacAddr,A3 ; |64|
LDBU .D1T1 *+A3(5),A5 ; |64|
;** --------------------------------------------------------------------------*
L9:
MVKL .S1 __remi,A3 ; |64|
|| LDBU .D1T1 *+A3(7),A4 ; |64|
;** --------------------------------------------------------------------------*
L10:
MVKH .S1 __remi,A3 ; |64|
MVK .S2 30,B5 ; |64|
CALL .S2X A3 ; |64|
ADDKPC .S2 RL3,B3,1 ; |64|
MPYUS .M1X A4,B5,A4 ; |64|
NOP 1
ADD .D1 A5,A4,A4 ; |64|
RL3: ; CALL OCCURS ; |64|
MVKL .S1 _sprintf,A3 ; |66|
MVKL .S2 _LocalIPAddr,B5 ; |66|
|| MVKH .S1 _sprintf,A3 ; |66|
MVKH .S2 _LocalIPAddr,B5 ; |66|
CALL .S2X A3 ; |66|
LDW .D2T1 *B5,A4 ; |66|
|| CMPGT .L1 A4,0,A0 ; |64|
|| MV .D1 A4,A5 ; |64|
MVKL .S2 SL6+0,B4 ; |66|
MVKH .S2 SL6+0,B4 ; |66|
STW .D2T2 B4,*+SP(4) ; |66|
|| [!A0] MVK .S1 0x64,A5 ; |65|
STW .D2T1 A5,*+SP(8) ; |66|
|| ADDKPC .S2 RL4,B3,0 ; |66|
RL4: ; CALL OCCURS ; |66|
BNOP .S1 L15,4 ; |66|
MV .D2 B13,B3 ; |68|
; BRANCH OCCURS ; |66|
;** --------------------------------------------------------------------------*
L11:
LDB .D2T2 *B5,B0 ; |186|
NOP 2
LDW .D2T2 *B6,B4 ; |183|
STDW .D1T1 A5:A4,*A3 ; |56|
[!B0] BNOP .S1 L15,3 ; |186|
[!B0] MV .S2 B13,B3 ; |68|
STB .D2T2 B0,*B4 ; |186|
; BRANCH OCCURS ; |186|
;** --------------------------------------------------------------------------*
MVC .S2 CSR,B7
LDB .D2T2 *++B5,B0 ; |186| (P) <0,0> ^
|| AND .S2 -2,B7,B6
MVC .S2 B6,CSR ; interrupts off
;*----------------------------------------------------------------------------*
;* SOFTWARE PIPELINE INFORMATION
;*
;* Loop source line : 186
;* Loop closing brace source line : 186
;* Known Minimum Trip Count : 1
;* Known Max Trip Count Factor : 1
;* Loop Carried Dependency Bound(^) : 1
;* Unpartitioned Resource Bound : 1
;* Partitioned Resource Bound(*) : 2
;* Resource Partition:
;* A-side B-side
;* .L units 0 0
;* .S units 1 0
;* .D units 0 2*
;* .M units 0 0
;* .X cross paths 0 0
;* .T address paths 0 2*
;* Long read paths 0 0
;* Long write paths 0 0
;* Logical ops (.LS) 0 0 (.L or .S unit)
;* Addition ops (.LSD) 1 0 (.L or .S or .D unit)
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