📄 dm642init.asm
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;******************************************************************************
;* TMS320C6x C/C++ Codegen PC Version 4.36 *
;* Date/Time created: Tue Dec 21 10:32:32 2004 *
;******************************************************************************
;******************************************************************************
;* GLOBAL FILE PARAMETERS *
;* *
;* Architecture : TMS320C64xx *
;* Optimization : Disabled *
;* Optimizing for : Compile time, Ease of Development *
;* Based on options: no -o, no -ms *
;* Endian : Little *
;* Interrupt Thrshld : Disabled *
;* Memory Model : Large *
;* Calls to RTS : Far *
;* Pipelining : Disabled *
;* Memory Aliases : Presume not aliases (optimistic) *
;* Debug Info : COFF Debug *
;* *
;******************************************************************************
.asg A15, FP
.asg B14, DP
.asg B15, SP
.global $bss
.file "dm642init.c"
.sect ".cinit"
.align 8
.field IR_1,32
.field _LinkStr+0,32
.field SL1,32 ; _LinkStr[0] @ 0
.field SL2,32 ; _LinkStr[1] @ 32
.field SL3,32 ; _LinkStr[2] @ 64
.field SL4,32 ; _LinkStr[3] @ 96
.field SL5,32 ; _LinkStr[4] @ 128
IR_1: .set 20
.sect ".text"
_LinkStr: .usect ".far",20,8
.sym _LinkStr,_LinkStr, 114, 3, 160,, 5
_bMacAddr: .usect ".far",8,8
.sym _bMacAddr,_bMacAddr, 60, 3, 64,, 8
; c:\ti\c6000\cgtools\bin\acp6x.exe -@C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp\TI1172_5
.sect ".text"
.global _dm642_init
.sym _dm642_init,_dm642_init, 32, 2, 0
.func 37
;******************************************************************************
;* FUNCTION NAME: _dm642_init *
;* *
;* Regs Modified : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,B0,B1,B2,B3,B4,B5,B6, *
;* B7,B8,B9,SP,A16,A17,A18,A19,A20,A21,A22,A23,A24, *
;* A25,A26,A27,A28,A29,A30,A31,B16,B17,B18,B19,B20, *
;* B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31 *
;* Regs Used : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,B0,B1,B2,B3,B4,B5,B6, *
;* B7,B8,B9,SP,A16,A17,A18,A19,A20,A21,A22,A23,A24, *
;* A25,A26,A27,A28,A29,A30,A31,B16,B17,B18,B19,B20, *
;* B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31 *
;* Local Frame Size : 0 Args + 0 Auto + 4 Save = 4 byte *
;******************************************************************************
_dm642_init:
;** --------------------------------------------------------------------------*
.line 2
STW .D2T2 B3,*SP--(8) ; |38|
NOP 2
.line 3
MVKL .S2 _CACHE_enableCaching,B4 ; |39|
MVKH .S2 _CACHE_enableCaching,B4 ; |39|
CALL .S2 B4 ; |39|
MVKL .S1 0x1848200,A4 ; |39|
ADDKPC .S2 RL0,B3,2 ; |39|
MVKH .S1 0x1848200,A4 ; |39|
RL0: ; CALL OCCURS ; |39|
.line 4
MVKL .S2 _CACHE_enableCaching,B4 ; |40|
MVKH .S2 _CACHE_enableCaching,B4 ; |40|
CALL .S2 B4 ; |40|
MVKL .S1 0x1848204,A4 ; |40|
ADDKPC .S2 RL1,B3,2 ; |40|
MVKH .S1 0x1848204,A4 ; |40|
RL1: ; CALL OCCURS ; |40|
.line 7
MVKL .S1 _EVMDM642_init,A3 ; |43|
MVKH .S1 _EVMDM642_init,A3 ; |43|
NOP 1
CALL .S2X A3 ; |43|
ADDKPC .S2 RL2,B3,4 ; |43|
RL2: ; CALL OCCURS ; |43|
.line 8
MVKL .S1 _EVMDM642_LED_init,A3 ; |44|
MVKH .S1 _EVMDM642_LED_init,A3 ; |44|
NOP 1
CALL .S2X A3 ; |44|
ADDKPC .S2 RL3,B3,4 ; |44|
RL3: ; CALL OCCURS ; |44|
.line 11
MVKL .S2 _EVMDM642_EEPROM_read,B5 ; |47|
MVKH .S2 _EVMDM642_EEPROM_read,B5 ; |47|
CALL .S2 B5 ; |47|
MVKL .S2 _bMacAddr,B4 ; |47|
MVKH .S2 _bMacAddr,B4 ; |47|
ADDKPC .S2 RL4,B3,0 ; |47|
MVK .S1 0x7f00,A4 ; |47|
MVK .D1 0x8,A6 ; |47|
RL4: ; CALL OCCURS ; |47|
.line 12
MVKL .S1 _bMacAddr,A3 ; |48|
MVKH .S1 _bMacAddr,A3 ; |48|
LDBU .D1T1 *A3,A5 ; |48|
MVK .S2 255,B4 ; |48|
MVKL .S1 _bMacAddr+1,A3 ; |48|
MVK .S1 255,A4 ; |48|
MVKH .S1 _bMacAddr+1,A3 ; |48|
CMPEQ .L1X A5,B4,A0 ; |48|
[!A0] BNOP .S1 L1,5 ; |48|
; BRANCH OCCURS ; |48|
;** --------------------------------------------------------------------------*
LDBU .D1T1 *A3,A3 ; |48|
NOP 4
CMPEQ .L1 A3,A4,A0 ; |48|
;** --------------------------------------------------------------------------*
L1:
CMPEQ .L1 A0,0,A0 ; |48|
[ A0] BNOP .S1 L2,2 ; |48|
MVKL .S1 _bMacAddr+2,A4 ; |48|
MVK .S1 255,A5 ; |48|
MVKH .S1 _bMacAddr+2,A4 ; |48|
|| XOR .D1 1,A0,A3 ; |48|
; BRANCH OCCURS ; |48|
;** --------------------------------------------------------------------------*
LDBU .D1T1 *A4,A3 ; |48|
NOP 4
CMPEQ .L1 A3,A5,A3 ; |48|
;** --------------------------------------------------------------------------*
L2:
CMPEQ .L1 A3,0,A0 ; |48|
[ A0] BNOP .S1 L3,3 ; |48|
MVKL .S1 _bMacAddr+3,A4 ; |48|
XOR .D1 1,A0,A3 ; |48|
|| MVKH .S1 _bMacAddr+3,A4 ; |48|
; BRANCH OCCURS ; |48|
;** --------------------------------------------------------------------------*
LDBU .D1T1 *A4,A3 ; |48|
NOP 4
CMPEQ .L1 A3,A5,A3 ; |48|
;** --------------------------------------------------------------------------*
L3:
CMPEQ .L1 A3,0,A0 ; |48|
[ A0] BNOP .S1 L4,3 ; |48|
MVKL .S1 _bMacAddr+4,A4 ; |48|
XOR .D1 1,A0,A3 ; |48|
|| MVKH .S1 _bMacAddr+4,A4 ; |48|
; BRANCH OCCURS ; |48|
;** --------------------------------------------------------------------------*
LDBU .D1T1 *A4,A3 ; |48|
NOP 4
CMPEQ .L1 A3,A5,A3 ; |48|
;** --------------------------------------------------------------------------*
L4:
CMPEQ .L1 A3,0,A0 ; |48|
[ A0] BNOP .S1 L5,3 ; |48|
MVKL .S1 _bMacAddr+5,A4 ; |48|
XOR .D1 1,A0,A3 ; |48|
|| MVKH .S1 _bMacAddr+5,A4 ; |48|
; BRANCH OCCURS ; |48|
;** --------------------------------------------------------------------------*
LDBU .D1T1 *A4,A3 ; |48|
NOP 4
CMPEQ .L1 A3,A5,A3 ; |48|
;** --------------------------------------------------------------------------*
L5:
CMPEQ .L1 A3,0,A1 ; |48|
[ A1] BNOP .S1 L6,2 ; |48|
MVKL .S1 _bMacAddr+6,A4 ; |48|
MVK .S1 255,A3 ; |48|
MVKH .S1 _bMacAddr+6,A4 ; |48|
|| XOR .D1 1,A1,A0 ; |48|
; BRANCH OCCURS ; |48|
;** --------------------------------------------------------------------------*
LDBU .D1T1 *A4,A4 ; |48|
NOP 4
CMPEQ .L1 A4,A3,A0 ; |48|
;** --------------------------------------------------------------------------*
L6:
[!A0] BNOP .S1 L7,2 ; |48|
MVKL .S2 _bMacAddr+7,B4 ; |48|
MVK .S2 255,B6 ; |48|
MVKH .S2 _bMacAddr+7,B4 ; |48|
|| MV .D2X A0,B5 ; |48|
; BRANCH OCCURS ; |48|
;** --------------------------------------------------------------------------*
LDBU .D2T2 *B4,B4 ; |48|
NOP 4
CMPEQ .L2 B4,B6,B5 ; |48|
;** --------------------------------------------------------------------------*
L7:
MV .D1X B5,A0 ; |48|
[!A0] BNOP .S1 L8,5 ; |48|
; BRANCH OCCURS ; |48|
;** --------------------------------------------------------------------------*
.line 17
MVKL .S2 _bMacAddr,B4 ; |53|
MVKL .S2 _bMacAddr+1,B5 ; |53|
MVKH .S2 _bMacAddr,B4 ; |53|
|| MVK .S1 68,A3 ; |53|
MVK .D1 4,A3 ; |53|
|| STB .D2T1 A3,*B4 ; |53|
|| MVKH .S2 _bMacAddr+1,B5 ; |53|
STB .D2T1 A3,*B5 ; |53|
NOP 2
.line 18
MVKL .S2 _bMacAddr+2,B5 ; |54|
MVKL .S2 _bMacAddr+3,B4 ; |54|
MVKH .S2 _bMacAddr+2,B5 ; |54|
|| MVK .S1 65,A3 ; |54|
MVK .L2 1,B5 ; |54|
|| STB .D2T1 A3,*B5 ; |54|
|| MVKH .S2 _bMacAddr+3,B4 ; |54|
STB .D2T2 B5,*B4 ; |54|
NOP 2
.line 19
MVKL .S2 _bMacAddr+4,B4 ; |55|
MVKL .S2 _bMacAddr+5,B5 ; |55|
MVKH .S2 _bMacAddr+4,B4 ; |55|
|| MVK .S1 90,A3 ; |55|
MVK .L2 1,B4 ; |55|
|| STB .D2T1 A3,*B4 ; |55|
|| MVKH .S2 _bMacAddr+5,B5 ; |55|
STB .D2T2 B4,*B5 ; |55|
NOP 2
.line 20
MVKL .S2 _bMacAddr+6,B5 ; |56|
MVK .S2 65,B4 ; |56|
MVKH .S2 _bMacAddr+6,B5 ; |56|
|| MVKL .S1 _bMacAddr+7,A3 ; |56|
STB .D2T2 B4,*B5 ; |56|
|| MVKH .S1 _bMacAddr+7,A3 ; |56|
|| MVK .D1 1,A4 ; |56|
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