📄 s3c2410.h
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#include "hardware.h"/* * Memmory Controller */#define MEM_CTL_BASE 0x48000000#define bMEMCTL(Nb) __REGl(MEM_CTL_BASE + (Nb))/* offset */#define oBWSCON 0x00#define oBANKCON0 0x04#define oBANKCON1 0x08#define oBANKCON2 0x0c#define oBANKCON3 0x10#define oBANKCON4 0x14#define oBANKCON5 0x18#define oBANKCON6 0x1c#define oBANKCON7 0x20#define oREFRESH 0x24#define oBANKSIZE 0x28#define oMRSRB6 0x2c#define oMRSRB7 0x30/* Registers */#define BWSCON bMEMCTL(oBWSCON)#define BANKCON0 bMEMCTL(oBANKCON0)#define BANKCON1 bMEMCTL(oBANKCON1)#define BANKCON2 bMEMCTL(oBANKCON2)#define BANKCON3 bMEMCTL(oBANKCON3)#define BANKCON4 bMEMCTL(oBANKCON4)#define BANKCON5 bMEMCTL(oBANKCON5)#define BANKCON6 bMEMCTL(oBANKCON6)#define BANKCON7 bMEMCTL(oBANKCON7)#define REFRESH bMEMCTL(oREFRESH)#define BANKSIZE bMEMCTL(oBANKSIZE)#define MRSRB6 bMEMCTL(oMRSRB6)#define MRSRB7 bMEMCTL(oMRSRB7)/* * GPIO */#define GPIO_CTL_BASE 0x56000000#define bGPIO(p, o) __REGl(GPIO_CTL_BASE + (p) + (o))/* offset */#define oGPIO_CON 0x0#define oGPIO_DAT 0x4#define oGPIO_UP 0x8 #define oGPIO_F 0x50#define oGPIO_H 0x70/* Registers */#define GPFCON bGPIO(oGPIO_F, oGPIO_CON)#define GPFDAT bGPIO(oGPIO_F, oGPIO_DAT)#define GPFUP bGPIO(oGPIO_F, oGPIO_UP)#define GPHCON bGPIO(oGPIO_H, oGPIO_CON)#define GPHDAT bGPIO(oGPIO_H, oGPIO_DAT)#define GPHUP bGPIO(oGPIO_H, oGPIO_UP)/* * UART */#define UART_CTL_BASE 0x50000000#define UART0_CTL_BASE UART_CTL_BASE#define bUART(x, Nb) __REGl(UART_CTL_BASE + (x)*0x4000 + (Nb))#define bUARTb(x, Nb) __REGb(UART_CTL_BASE + (x)*0x4000 + (Nb))/* offset */#define oULCON 0x00#define oUCON 0x04#define oUFCON 0x08#define oUMCON 0x0c#define oUTRSTAT 0x10#define oUERSTAT 0x14#define oUFSTAT 0x18#define oUMSTAT 0x1c#define oUTXHL 0x20#define oUTXHB 0x23#define oURXHL 0x24#define oURXHB 0x27#define oUBRDIV 0x28/* Registers */#define ULCON0 bUART(0, oULCON)#define UCON0 bUART(0, oUCON)#define UFCON0 bUART(0, oUFCON)#define UMCON0 bUART(0, oUMCON)#define UTRSTAT0 bUART(0, oUTRSTAT)#define UERSTAT0 bUART(0, oUERSTAT)#define UFSTAT0 bUART(0, oUFSTAT)#define UMSTAT0 bUART(0, oUMSTAT)#define UTXH0 bUART(0, oUTXHL)#define URXH0 bUART(0, oURXHL)#define UBRDIV0 bUART(0, oUBRDIV)/* state */#define UTRSTAT_TX_EMPTY (1 << 2)#define UTRSTAT_RX_READY (1 << 0)#define UART_ERR_MASK 0x0f/* * Nand Flash Controller */#define NAND_CTL_BASE 0x4e000000#define bNAND_CTL(Nb) __REG(NAND_CTL_BASE + (Nb))/* offset */#define oNFCONF 0x00#define oNFCMD 0x04#define oNFADDR 0x08#define oNFDATA 0x0c#define oNFSTAT 0x10#define oNFECC 0x14/* Registers */#define NFCONF bNAND_CTL(oNFCONF)#define NFCMD bNAND_CTL(oNFCMD)#define NFADDR bNAND_CTL(oNFADDR)#define NFDATA bNAND_CTL(oNFDATA)#define NFSTAT bNAND_CTL(oNFSTAT)#define NFECC bNAND_CTL(oNFECC)/* * WDT */#define WDT_CTL_BASE 0x53000000#define bWDT_CTL(Nb) __REG(WDT_CTL_BASE + (Nb))/* offset */#define oWTCON 0x00#define oWTDAT 0x04#define oWTCNT 0x08/* Registers */#define WTCON bWDT_CTL(oWTCON)#define WTDAT bWDT_CTL(oWTDAT)#define WTCNT bWDT_CTL(oWTCNT)⌨️ 快捷键说明
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