head.s

英培特EDUKIT-III实验箱核心子板为s3c2410

/*
 * Name	: head.s
 * Disc	: startup code
 * 2007-08-03 by Qingmin Liu
 */

#include "s3c2410.h"
#include "machine.h"

@ Sdram
.equ SDRAM_BASE,	0x30000000

@ Stack top address
.equ stack_top,		0x34000000

@
@ start
@

.text
.global _start

_start:
	@ disable watch dog timer
	mov r0, #WTCON
	mov r1, #0x0
	str r1, [r0]

	@ memory setup
	bl memsetup

	@ copy the 4K code from steppingstone
	bl copy_myself

	ldr sp, =stack_top
	ldr lr, =stop
	ldr pc, =main

stop:
	b stop

@
@ sub routines
@

@
@ nand flash read
@

copy_myself:
	mov r10, lr

	@ inital
	mov r1, #NAND_CTL_BASE
	ldr r2, =0xf830		@ initial value
	str r2, [r1, #oNFCONF]

	@ reset nand flash
	ldr r2, [r1, #oNFCONF]
	bic r2, r2, #0x800	@ nFCE active
	str r2, [r1, #oNFCONF]
	mov r2, #0xff		@ reset command
	strb r2, [r1, #oNFCMD]

	@ delay
	mov r3, #0x0a
1:
	subs r3, r3, #1
	bne 1b

	@ wait idle state	
2:
	ldr r2, [r1, #oNFSTAT]
	tst r2, #0x01
	beq 2b

	ldr r2, [r1, #oNFCONF]
	orr r2, r2, #0x800	@ nFCE inactive
	str r2, [r1, #oNFCONF]

	ldr sp, =4096		@ nand_read.c needed
	ldr r0, =0x30000000	@ nand_read_ll argument 1
	mov r1, #4096		@ nand_read_ll argument 2
	mov r2, #0x3000		@ nand_read_ll argument 3
	bl nand_read_ll

	mov pc, r10

@ r1: memory control register base address
@ r2: memory control register table address
@ r3: r1+13 words(because there is 13 registers)

memsetup:
	mov     r1, #MEM_CTL_BASE
	adrl    r2, mem_cfg_val
	add     r3, r1, #13*4
1:
	@ write initial values to registers
	ldr     r4, [r2], #4
	str     r4, [r1], #4
	cmp     r1, r3
	bne     1b

        mov     pc, lr

.align 4
mem_cfg_val:
	.long vBWSCON		@ BWSCON
	.long vBANKCON0		@ BANKCON0
	.long vBANKCON1		@ BANKCON1
	.long vBANKCON2		@ BANKCON2
	.long vBANKCON3		@ BANKCON3
	.long vBANKCON4		@ BANKCON4
	.long vBANKCON5		@ BANKCON5
	.long vBANKCON6		@ BANKCON6
	.long vBANKCON7		@ BANKCON7
	.long vREFRESH		@ REFRESH
	.long vBANKSIZE		@ BANKSIZE
	.long vMRSRB6		@ MRSRB6
	.long vMRSRB7		@ MRSRB7

.end