cs8900.h

增加了tftp功能的vivi代码

#define CS8900_BASE 0x19000300

#define CS8900_BUS16_0 				 *(volatile u8 *)(CS8900_BASE+0x00)
#define CS8900_BUS16_1 				 *(volatile u8 *)(CS8900_BASE+0x01)


#define CS8900_Receive_TransmitData 	*(volatile u16 *)(CS8900_BASE+0x00)
#define CS8900_TxCMD 				    *(volatile u16 *)(CS8900_BASE+0x04)
#define CS8900_TxLength  				*(volatile u16 *)(CS8900_BASE+0x06)
#define CS8900_InterruptStatusQueue     *(volatile u16 *)(CS8900_BASE+0x08)
#define CS8900_PacketPageRegister   	*(volatile u16 *)(CS8900_BASE+0x0A)
#define CS8900_PacketPageData  			*(volatile u16 *)(CS8900_BASE+0x0C)


#define InterruptStatusQueue_RxEvent     0x04
#define InterruptStatusQueue_TxEvent     0x08
#define InterruptStatusQueue_BufEvent    0x0C
#define InterruptStatusQueue_RxMissEvent 0x10
#define InterruptStatusQueue_TxColEvent  0x12
#define InterruptStatusQueue_EventMask   0x3F

/* packet page register offsets */

/* bus interface registers */
#define PacketPageRegister_ChipID              0x0000  // Chip identifier - must be 0x630E
#define PacketPageRegister_ChipRev  		   0x0002  // Chip revision, model codes

#define PacketPageRegister_IntReg    		   0x0022  // Interrupt configuration
#define PacketPageRegister_IntReg_IRQ0         0x0000  // Use INTR0 pin
#define PacketPageRegister_IntReg_IRQ1         0x0001  // Use INTR1 pin
#define PacketPageRegister_IntReg_IRQ2         0x0002  // Use INTR2 pin
#define PacketPageRegister_IntReg_IRQ3         0x0003  // Use INTR3 pin

/* status and control registers */

#define PacketPageRegister_RxCFG  			   0x0102  // Receiver configuration
#define PacketPageRegister_RxCFG_Skip1         0x0040  // Skip (i.e. discard) current frame
#define PacketPageRegister_RxCFG_Stream        0x0080  // Enable streaming mode
#define PacketPageRegister_RxCFG_RxOK          0x0100  // RxOK interrupt enable
#define PacketPageRegister_RxCFG_RxDMAonly     0x0200  // Use RxDMA for all frames
#define PacketPageRegister_RxCFG_AutoRxDMA     0x0400  // Select RxDMA automatically
#define PacketPageRegister_RxCFG_BufferCRC     0x0800  // Include CRC characters in frame
#define PacketPageRegister_RxCFG_CRC           0x1000  // Enable interrupt on CRC error
#define PacketPageRegister_RxCFG_RUNT          0x2000  // Enable interrupt on RUNT frames
#define PacketPageRegister_RxCFG_EXTRA         0x4000  // Enable interrupt on frames with extra data

#define PacketPageRegister_RxCTL    		   0x0104  // Receiver control
#define PacketPageRegister_RxCTL_IAHash        0x0040  // Accept frames that match hash
#define PacketPageRegister_RxCTL_Promiscuous   0x0080  // Accept any frame
#define PacketPageRegister_RxCTL_RxOK          0x0100  // Accept well formed frames
#define PacketPageRegister_RxCTL_Multicast     0x0200  // Accept multicast frames
#define PacketPageRegister_RxCTL_IA            0x0400  // Accept frame that matches IA
#define PacketPageRegister_RxCTL_Broadcast     0x0800  // Accept broadcast frames
#define PacketPageRegister_RxCTL_CRC           0x1000  // Accept frames with bad CRC
#define PacketPageRegister_RxCTL_RUNT          0x2000  // Accept runt frames
#define PacketPageRegister_RxCTL_EXTRA         0x4000  // Accept frames that are too long

#define PacketPageRegister_TxCFG     		   0x0106  // Transmit configuration
#define PacketPageRegister_TxCFG_CRS           0x0040  // Enable interrupt on loss of carrier
#define PacketPageRegister_TxCFG_SQE           0x0080  // Enable interrupt on Signal Quality Error
#define PacketPageRegister_TxCFG_TxOK          0x0100  // Enable interrupt on successful xmits
#define PacketPageRegister_TxCFG_Late          0x0200  // Enable interrupt on "out of window" 
#define PacketPageRegister_TxCFG_Jabber        0x0400  // Enable interrupt on jabber detect
#define PacketPageRegister_TxCFG_Collision     0x0800  // Enable interrupt if collision
#define PacketPageRegister_TxCFG_16Collisions  0x8000  // Enable interrupt if > 16 collisions

#define PacketPageRegister_TxCmd    		   0x0108  // Transmit command status
#define PacketPageRegister_TxCmd_TxStart_5     0x0000  // Start after 5 bytes in buffer
#define PacketPageRegister_TxCmd_TxStart_381   0x0040  // Start after 381 bytes in buffer
#define PacketPageRegister_TxCmd_TxStart_1021  0x0080  // Start after 1021 bytes in buffer
#define PacketPageRegister_TxCmd_TxStart_Full  0x00C0  // Start after all bytes loaded
#define PacketPageRegister_TxCmd_Force         0x0100  // Discard any pending packets
#define PacketPageRegister_TxCmd_OneCollision  0x0200  // Abort after a single collision
#define PacketPageRegister_TxCmd_NoCRC         0x1000  // Do not add CRC
#define PacketPageRegister_TxCmd_NoPad         0x2000  // Do not pad short packets

#define PacketPageRegister_BufCFG 			   0x010A  // Buffer configuration
#define PacketPageRegister_BufCFG_SWI          0x0040  // Force interrupt via software
#define PacketPageRegister_BufCFG_RxDMA        0x0080  // Enable interrupt on Rx DMA
#define PacketPageRegister_BufCFG_TxRDY        0x0100  // Enable interrupt when ready for Tx
#define PacketPageRegister_BufCFG_TxUE         0x0200  // Enable interrupt in Tx underrun
#define PacketPageRegister_BufCFG_RxMiss       0x0400  // Enable interrupt on missed Rx packets
#define PacketPageRegister_BufCFG_Rx128        0x0800  // Enable Rx interrupt after 128 bytes
#define PacketPageRegister_BufCFG_TxCol        0x1000  // Enable int on Tx collision ctr overflow
#define PacketPageRegister_BufCFG_Miss         0x2000  // Enable int on Rx miss ctr overflow
#define PacketPageRegister_BufCFG_RxDest       0x8000  // Enable int on Rx dest addr match

#define PacketPageRegister_LineCTL 			   0x0112  // Line control
#define PacketPageRegister_LineCTL_Rx          0x0040  // Enable receiver
#define PacketPageRegister_LineCTL_Tx          0x0080  // Enable transmitter
#define PacketPageRegister_LineCTL_AUIonly     0x0100  // AUI interface only
#define PacketPageRegister_LineCTL_AutoAUI10BT 0x0200  // Autodetect AUI or 10BaseT interface
#define PacketPageRegister_LineCTL_ModBackoffE 0x0800  // Enable modified backoff algorithm
#define PacketPageRegister_LineCTL_PolarityDis 0x1000  // Disable Rx polarity autodetect
#define PacketPageRegister_LineCTL_2partDefDis 0x2000  // Disable two-part defferal
#define PacketPageRegister_LineCTL_LoRxSquelch 0x4000  // Reduce receiver squelch threshold

#define PacketPageRegister_SelfCTL			   0x0114  // Chip self control
#define PacketPageRegister_SelfCTL_Reset       0x0040  // Self-clearing reset
#define PacketPageRegister_SelfCTL_SWSuspend   0x0100  // Initiate suspend mode
#define PacketPageRegister_SelfCTL_HWSleepE    0x0200  // Enable SLEEP input
#define PacketPageRegister_SelfCTL_HWStandbyE  0x0400  // Enable standby mode
#define PacketPageRegister_SelfCTL_HC0E        0x1000  // use HCB0 for LINK LED
#define PacketPageRegister_SelfCTL_HC1E        0x2000  // use HCB1 for BSTATUS LED
#define PacketPageRegister_SelfCTL_HCB0        0x4000  // control LINK LED if HC0E set
#define PacketPageRegister_SelfCTL_HCB1        0x8000  // control BSTATUS LED if HC1E set

#define PacketPageRegister_BusCTL    		   0x0116  // Bus control
#define PacketPageRegister_BusCTL_ResetRxDMA   0x0040  // Reset RxDMA pointer
#define PacketPageRegister_BusCTL_DMAextend    0x0100  // Extend DMA cycle
#define PacketPageRegister_BusCTL_UseSA        0x0200  // Assert MEMCS16 on address decode
#define PacketPageRegister_BusCTL_MemoryE      0x0400  // Enable memory mode
#define PacketPageRegister_BusCTL_DMAburst     0x0800  // Limit DMA access burst
#define PacketPageRegister_BusCTL_IOCHRDYE     0x1000  // Set IOCHRDY high impedence
#define PacketPageRegister_BusCTL_RxDMAsize    0x2000  // Set DMA buffer size 64KB
#define PacketPageRegister_BusCTL_EnableIRQ    0x8000  // Generate interrupt on interrupt event 

#define PacketPageRegister_TestCTL  		   0x0118  // Test control
#define PacketPageRegister_TestCTL_DisableLT   0x0080  // Disable link status 
#define PacketPageRegister_TestCTL_ENDECloop   0x0200  // Internal loopback
#define PacketPageRegister_TestCTL_AUIloop     0x0400  // AUI loopback
#define PacketPageRegister_TestCTL_DisBackoff  0x0800  // Disable backoff algorithm
#define PacketPageRegister_TestCTL_FDX         0x4000  // Enable full duplex mode

#define PacketPageRegister_InterruptStatusQueue       0x0120  // Interrupt Status Queue

#define PacketPageRegister_RER      		   0x0124  // Receive event
#define PacketPageRegister_RER_IAHash          0x0040  // Frame hash match
#define PacketPageRegister_RER_Dribble         0x0080  // Frame had 1-7 extra bits after last byte
#define PacketPageRegister_RER_RxOK            0x0100  // Frame received with no errors
#define PacketPageRegister_RER_Hashed          0x0200  // Frame address hashed OK
#define PacketPageRegister_RER_IA              0x0400  // Frame address matched IA
#define PacketPageRegister_RER_Broadcast       0x0800  // Broadcast frame
#define PacketPageRegister_RER_CRC             0x1000  // Frame had CRC error
#define PacketPageRegister_RER_RUNT            0x2000  // Runt frame
#define PacketPageRegister_RER_EXTRA           0x4000  // Frame was too long

#define PacketPageRegister_TER      		   0x0128 // Transmit event
#define PacketPageRegister_TER_CRS             0x0040  // Carrier lost
#define PacketPageRegister_TER_SQE             0x0080  // Signal Quality Error
#define PacketPageRegister_TER_TxOK            0x0100  // Packet sent without error
#define PacketPageRegister_TER_Late            0x0200  // Out of window
#define PacketPageRegister_TER_Jabber          0x0400  // Stuck transmit?
#define PacketPageRegister_TER_NumCollisions   0x7800  // Number of collisions
#define PacketPageRegister_TER_16Collisions    0x8000  // > 16 collisions

#define PacketPageRegister_BER      		   0x012C // Buffer event
#define PacketPageRegister_BER_SWint           0x0040 // Software interrupt
#define PacketPageRegister_BER_RxDMAFrame      0x0080 // Received framed DMAed
#define PacketPageRegister_BER_Rdy4Tx          0x0100 // Ready for transmission
#define PacketPageRegister_BER_TxUnderrun      0x0200 // Transmit underrun
#define PacketPageRegister_BER_RxMiss          0x0400 // Received frame missed
#define PacketPageRegister_BER_Rx128           0x0800 // 128 bytes received
#define PacketPageRegister_BER_RxDest          0x8000 // Received framed passed address filter

#define PacketPageRegister_RxMiss   		   0x0130  //  Receiver miss counter 

#define PacketPageRegister_TxCol               0x0132  //  Transmit collision counter

#define PacketPageRegister_LineSTAT 		   0x0134  // Line status
#define PacketPageRegister_LineSTAT_LinkOK     0x0080  // Line is connected and working
#define PacketPageRegister_LineSTAT_AUI        0x0100  // Connected via AUI
#define PacketPageRegister_LineSTAT_10BT       0x0200  // Connected via twisted pair
#define PacketPageRegister_LineSTAT_Polarity   0x1000  // Line polarity OK (10BT only)
#define PacketPageRegister_LineSTAT_CRS        0x4000  // Frame being received

#define PacketPageRegister_SelfSTAT  		   0x0136  // Chip self status
#define PacketPageRegister_SelfSTAT_33VActive  0x0040  // suPacketPageRegisterly voltage is 3.3V
#define PacketPageRegister_SelfSTAT_InitD      0x0080  // Chip initialization complete
#define PacketPageRegister_SelfSTAT_SIBSY      0x0100  // EEPROM is busy
#define PacketPageRegister_SelfSTAT_EEPROM     0x0200  // EEPROM present
#define PacketPageRegister_SelfSTAT_EEPROM_OK  0x0400  // EEPROM checks out
#define PacketPageRegister_SelfSTAT_ELPresent  0x0800  // External address latch logic available
#define PacketPageRegister_SelfSTAT_EEsize     0x1000  // Size of EEPROM

#define PacketPageRegister_BusSTAT             0x0138  // Bus status
#define PacketPageRegister_BusSTAT_TxBid       0x0080  // Tx error
#define PacketPageRegister_BusSTAT_TxRDY       0x0100  // Ready for Tx data

#define PacketPageRegister_TDR                 0x013C  // AUI Time Domain Reflectometer

/* initiate transmit registers */

#define PacketPageRegister_TxCommand 		   0x0144  // Tx Command 
#define PacketPageRegister_TxLength            0x0146  // Tx Length 


/* address filter registers */

#define PacketPageRegister_LAF      		   0x0150  // Logical address filter (6 bytes)
#define PacketPageRegister_IA                  0x0158  // Individual address (MAC)

/* EEPROM Kram */
#define SI_BUSY 							   0x0100
#define PacketPageRegister_SelfST			   0x0136	/*  Self State register */
#define PacketPageRegister_EECMD			   0x0040		/*  NVR Interface Command register */
#define PacketPageRegister_EEData 			   0x0042	/*  NVR Interface Data Register */
#define EEPROM_WRITE_EN		                   0x00F0
#define EEPROM_WRITE_DIS					   0x0000
#define EEPROM_WRITE_CMD					   0x0100
#define EEPROM_READ_CMD					       0x0200

void eth_init( void );
void eth_halt(void);
int eth_send(volatile void *packet, int length);
int eth_rx(void);