📄 mode_iii.c
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/************************************************************/
/* FILENAME: mode_III.c */
/* DESCRIPTION: This program uses Mcbsp1 to read 512 x 2ch */
/* samples continuously from the ADS8361 in Mode III. The */
/* SPI Port is configured as a slave device to receive 512 */
/* x 2 ch from the serial Data B pin. */
/* */
/* AUTHOR : DAP Application Group, T. Hendrick, Dallas */
/* CREATED 2003(C) BY TEXAS INSTRUMENTS INCORPORATED. */
/* VERSION: 1.0 */
/************************************************************/
// Program assumes M1 static logic low by means of jumpers on
// EVM. M0 is toggled by GPIO
// The McBSP CLKr signal is tied to the SPI SCLK, Serial B out
// ties back to the SPI port via SIMO
#include "DSP28_Device.h"
#include "DSP28_Globalprototypes.h"
// Global Variables
#define Samples 512
#define Channels 4
long AD_temp0, AD_temp1, AD_temp2;
int idx = 0, ch;
unsigned int ch0 = 0x0000, ch1 = 0x4000;
unsigned int dummy = 0x0000;
unsigned int SPI_UB_Temp;
unsigned int SPI_LB_Temp;
unsigned int SPI_Data[Channels/2][Samples];
unsigned int McBSP_Data[Channels/2][Samples];
// Prototype statements for functions found within this file.
void delay_loop(int count);
void spi_init(void);
void spi_fifo_init(void);
void spi_fifo_enable(void);
void spi_xmit(void);
void mcbsp_init(void);
void mcbsp_xmit(int a, int b);
// Prototype statements for GPIO functions found within this file.
void Toggle_M0(int);
void Toggle_CS(int);
void Toggle_STE(int);
void SYNC_UP(void);
void main(void)
{
// Initialize System Control registers, PLL, WatchDog, Clocks to default state:
// This function is found in the DSP28_SysCtrl.c file.
InitSysCtrl();
// Select GPIO for the device or for the specific application:
// This function is found in the DSP28_Gpio.c file.
// InitGpio(); skip this as this is example selects the I/O for McBSP in this file itself
InitGpio();
// Initialize PIE vector table:
// The PIE vector table is initialized with pointers to shell Interrupt
// Service Routines (ISR). The shell routines are found in DSP28_DefaultIsr.c.
// Insert user specific ISR code in the appropriate shell ISR routine in
// the DSP28_DefaultIsr.c file.
// Disable and clear all CPU interrupts:
DINT;
IER = 0x0000;
IFR = 0x0000;
// Initialize Pie Control Registers To Default State:
// This function is found in the DSP28_PieCtrl.c file.
InitPieCtrl();
// Initialize the PIE Vector Table To a Known State:
// This function is found in DSP28_PieVect.c.
// This function populates the PIE vector table with pointers
// to the shell ISR functions found in DSP28_DefaultIsr.c.
InitPieVectTable();
// User specific functions, Reassign vectors, Enable Interrupts, etc:
EALLOW;
GpioMuxRegs.GPEMUX.all=0x0000; // Select GPIOs to be McBSP pins
GpioMuxRegs.GPEDIR.all=0x0001; // Select GPIOF3 as OUT, /CS to ADC
GpioMuxRegs.GPFMUX.all=0x7F07; //(0x7F00 | 0x0007); // Select GPIOs to be McBSP pins
GpioMuxRegs.GPFDIR.all=0x0008; // Select GPIOF3 as OUT, /CS to ADC
GpioMuxRegs.GPAMUX.all=0x0000; // Select GPIOA2 & 3 for FSx and FSr
GpioMuxRegs.GPADIR.all=0x0004; // Select GPIOA2 as OUT, 3 as IN
EDIS;
spi_init();
spi_fifo_init();
mcbsp_init();
while(1) // Forever Loop
{
SYNC_UP();
spi_fifo_enable();
Toggle_STE(0);
for(idx=0; idx<Samples; idx++)
{
for(ch=0; ch<Channels/2; ch++)
{
mcbsp_xmit(ch0, dummy);
while(McbspaRegs.SPCR1.bit.RRDY != 1) { }
// Wait for McBSP FIFO receive ready
AD_temp1 = McbspaRegs.DRR2.all; // Receive Channel data and MSB
AD_temp0 = McbspaRegs.DRR1.all; // Receive 15 LSB's
// Format Data
AD_temp2 = ((AD_temp1<<16)&0xFFFFFFFF | (AD_temp0 &0xFFFFFFFF));
McBSP_Data[ch][idx] = (AD_temp2)>>1 ; // Store Formatted serial data
while(SpiaRegs.SPIFFRX.bit.RXFFST ==0) { }
SPI_LB_Temp = SpiaRegs.SPIRXBUF>>13;
SPI_UB_Temp = SpiaRegs.SPIRXBUF<<3;
// SPI_Data[ch][idx] = (SPI_UB_Temp + SPI_LB_Temp);
SPI_Data[ch][idx] = (SPI_UB_Temp + SPI_LB_Temp);
delay_loop(15);
}
}
Toggle_STE(1); // Clear M1
} // End of loop - add Probe Point here to view data array
}
// Some Useful local functions
void delay_loop(int count)
{
long i;
for (i = 0; i < count; i++) {}
}
void SYNC_UP()
{
Toggle_STE(1); // Clear M1
Toggle_M0(0);
McbspaRegs.SPCR2.bit.FRST = 1;
mcbsp_xmit(ch0, dummy);
while(McbspaRegs.SPCR1.bit.RRDY != 1) { }
// Wait for McBSP FIFO receive ready
AD_temp1 = McbspaRegs.DRR2.all; // Receive Channel data and MSB
AD_temp0 = McbspaRegs.DRR1.all; // Receive 15 LSB's
delay_loop(15);
Toggle_M0(1);
mcbsp_xmit(ch0, dummy);
while(McbspaRegs.SPCR1.bit.RRDY != 1) { }
// Wait for McBSP FIFO receive ready
AD_temp1 = McbspaRegs.DRR2.all; // Receive Channel data and MSB
AD_temp0 = McbspaRegs.DRR1.all; // Receive 15 LSB's
delay_loop(15);
// Release Reset for SPI
SpiaRegs.SPICCR.all =0x008F;
}
void spi_xmit()
{
SpiaRegs.SPITXBUF = 0x8000;
while(SpiaRegs.SPIFFTX.bit.TXFFST !=0) { }
SpiaRegs.SPITXBUF = 0x0000;
while(SpiaRegs.SPIFFTX.bit.TXFFST !=0) { }
}
void spi_init()
{
SpiaRegs.SPICCR.all =0x000F; // Reset on, rising edge, 16-bit char bits
SpiaRegs.SPICTL.all =0x0003; // Enable master mode, normal phase,
}
void spi_fifo_init()
{
// Initialize SPI FIFO registers
SpiaRegs.SPIFFTX.all=0x0040;
SpiaRegs.SPIFFRX.all=0x0040;
SpiaRegs.SPIFFCT.all=0x00;
}
void spi_fifo_enable()
{
// Initialize SPI FIFO registers
SpiaRegs.SPIFFTX.all |=0xC040;
SpiaRegs.SPIFFRX.all |=0x6062;
}
void mcbsp_init()
{
McbspaRegs.SPCR2.all=0x0000; // XRST =0
McbspaRegs.SPCR1.all=0x0200; // RRST =0, DLB enabled
McbspaRegs.RCR2.all=0x0;
McbspaRegs.RCR1.all=0x0;
McbspaRegs.XCR2.all=0x0;
McbspaRegs.XCR1.all=0x0;
McbspaRegs.SRGR2.all=0x200f;
McbspaRegs.SRGR1.all=0x0001;
McbspaRegs.MCR2.all=0x0;
McbspaRegs.MCR1.all=0x0;
McbspaRegs.PCR1.all=0x0a00;
// Bit changes for the test
McbspaRegs.SPCR1.bit.RJUST =00; // word Rjustifed
McbspaRegs.SPCR1.bit.CLKSTP =10; // word Rjustifed
McbspaRegs.SRGR2.bit.FSGM=0; // FSGM =1 for FSX based on write to DXR -XSR
// has to be set FWID to work!
McbspaRegs.SRGR2.bit.FPER =32; // set FPER = 21
McbspaRegs.SRGR1.bit.CLKGDV =03; // set CLKGDV = 3
McbspaRegs.SRGR1.bit.FWID =03; // set Fwidth =8
McbspaRegs.RCR2.bit.RCOMPAND =00; // No R/XCOMPAND
McbspaRegs.RCR2.bit.RDATDLY =00;
McbspaRegs.XCR2.bit.XCOMPAND =00;
McbspaRegs.XCR2.bit.XDATDLY =00;
McbspaRegs.RCR1.bit.RWDLEN1 =3; // 16-bit word
McbspaRegs.XCR1.bit.XWDLEN1 =5; // 16-bit word
// McBSP Reset to enable
McbspaRegs.SPCR2.bit.XRST =1;
McbspaRegs.SPCR1.bit.RRST =1;
// delay_loop(100);
McbspaRegs.SPCR2.all |=0x0040; // Only enable FRST,GRST used after
}
void mcbsp_xmit(int a, int b)
{ while(McbspaRegs.SPCR2.bit.XRDY ==0) { }
McbspaRegs.DXR2.all=a;
McbspaRegs.DXR1.all=b;
}
void Toggle_CS(int state)
{
switch(state)
{
case 0:
GpioDataRegs.GPACLEAR.all = 0x0004; // Test Clear
break;
case 1:
GpioDataRegs.GPASET.all = 0x0004; // Test Set
break;
}
}
void Toggle_STE(int state)
{
switch(state)
{
case 0:
GpioDataRegs.GPFCLEAR.all = 0x0008; // Clear M0
break;
case 1:
GpioDataRegs.GPFSET.all = 0x0008; // Set M0 High
break;
}
}
void Toggle_M0(int state)
{
switch(state)
{
case 0:
GpioDataRegs.GPACLEAR.all = 0x0004; // Clear M0
break;
case 1:
GpioDataRegs.GPASET.all = 0x0004; // Set M0 High
break;
}
}
//===========================================================================
// End Program.
//===========================================================================
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