mode_iv.c

Welcome to the software files for the ADS8361 to TMS320F2812! There are two project files in each

/************************************************************/
/* FILENAME: mode_IV.c                            			*/
/* DESCRIPTION: This program uses Mcbsp1 to read 512 		*/
/*	samples continuously from the ADS8361 in Mode IV.   	*/
/*	Four channels are displayed sequentially, starting at A0.*/
/*	Data is recieved by the McBSP from the DATA_A pin.      */         
/* AUTHOR	: DAP Application Group, T. Hendrick, Dallas    */
/*    CREATED 2002(C) BY TEXAS INSTRUMENTS INCORPORATED.  	*/
/* VERSION: 1.0 							                */
/************************************************************/

/* Note:  This program assumes A0, M0 and M1 are controlled via GPIO
functions of PORT F!! */

#include "DSP28_Device.h"
#include "DSP28_Globalprototypes.h"

// Global Variables
#define Samples 512
#define Channels  4
 
int idx = 0;
long ch = 0;
long var1 = 0;

long AD_temp0, AD_temp1, AD_temp2;
unsigned int ADC_Data[Channels][Samples];

// Prototype statements for functions found within this file.
void delay_loop(int count);
void mcbsp_init(void);
void mcbsp_xmit(int a);

// Prototype statements for GPIO functions found within this file.
void Toggle_A0(int);
void Toggle_CS(int);
void Toggle_Ms(int);
void Toggle_M0(int);
void Toggle_M1(int);
void SYNC_UP(void);
void main(void)
{

// Initialize System Control registers, PLL, WatchDog, Clocks to default state:
    // This function is found in the DSP28_SysCtrl.c file.
    InitSysCtrl();

// Select GPIO for the device or for the specific application:
    // This function is found in the DSP28_Gpio.c file.
    // InitGpio(); skip this as this is example selects the I/O for McBSP in this file itself
     InitGpio();   

// Initialize PIE vector table:
    // The PIE vector table is initialized with pointers to shell Interrupt 
    // Service Routines (ISR).  The shell routines are found in DSP28_DefaultIsr.c.
    // Insert user specific ISR code in the appropriate shell ISR routine in 
    // the DSP28_DefaultIsr.c file.

    // Disable and clear all CPU interrupts:
    DINT;
    IER = 0x0000;
    IFR = 0x0000;

    // Initialize Pie Control Registers To Default State:
        // This function is found in the DSP28_PieCtrl.c file.
    InitPieCtrl();

    // Initialize the PIE Vector Table To a Known State:
    // This function is found in DSP28_PieVect.c.
    // This function populates the PIE vector table with pointers
    // to the shell ISR functions found in DSP28_DefaultIsr.c.
    InitPieVectTable();    
    
// User specific functions, Reassign vectors, Enable Interrupts, etc:
    EALLOW;
    GpioMuxRegs.GPEMUX.all=0x0000;    // Select Port E as GPIOs     
    GpioMuxRegs.GPEDIR.all=0x0001;    // Select Port E.1 as Output
    GpioMuxRegs.GPFMUX.all=0x7F00;    // Select Port F to be McBSP     
    GpioMuxRegs.GPFDIR.all=0x000F;    // Select Port F.1-4 as GP Outs
    EDIS;
//    mcbsp_fifo_init();                                  // Initialize the Mcbsp FIFO
    mcbsp_init();                                       // Initialize the Mcbsp

while(1)                                                // Forever Loop
	{
	SYNC_UP();
//  Get Conversions Synchronized with CHAx
    McbspaRegs.SPCR2.bit.FRST = 1;
//	Start Frame Sync;
	Toggle_CS(0);	
	for(idx=0; idx<Samples; idx++)
		{
 		for(ch=0; ch<Channels; ch++)
		{
// Toggle_RD_CONVST via Frame Sync;        
	while(McbspaRegs.SPCR1.bit.RRDY != 1) { }
// Wait for McBSP FIFO receive ready
	    AD_temp1 = McbspaRegs.DRR2.all;        // Receive Channel data and MSB
	    AD_temp0 = McbspaRegs.DRR1.all;        // Receive 15 LSB's
//	    while(McbspaRegs.MFFRX.bit.ST==0) { }
        AD_temp2 = ((AD_temp1<<16)&0xFFFFFFFF | (AD_temp0 &0xFFFFFFFF));
	    ADC_Data[ch][idx] = (AD_temp2)>>1 ;    // Store Formatted serial data
	    }
	   }
    McbspaRegs.SPCR2.bit.FRST = 0;
//	Toggle_CS(1);
    delay_loop(50);
	}  //End of Smaple Loop - place probe point here to view data array
}     

// Some Useful local functions
void delay_loop(int count)
{
	int i;
    for (i = 0; i < count; i++) {}
}


// McBSP Setup - 16-bit word, trailing LSBs are 00
//         Internal clocks, Frame sync on  DXR-XSR write
//         CLKX = LSPCLK/16, CLKGDIV =03, CLKR internal tied to CLKR
//         Delay transmit and recieve by 1 bit (Valid data on 1st falling
//             CLKX/CLKR edge after FSX/FSR)

void mcbsp_init()
{
    McbspaRegs.SPCR2.all=0x0000;                        // XRST =0
    McbspaRegs.SPCR1.all=0x0200;                        // RRST =0, DLB enabled
    McbspaRegs.RCR2.all=0x0;
    McbspaRegs.RCR1.all=0x0;
    McbspaRegs.XCR2.all=0x0;
    McbspaRegs.XCR1.all=0x0;
    McbspaRegs.SRGR2.all=0x200f;                      
    McbspaRegs.SRGR1.all=0x0001;
    McbspaRegs.MCR2.all=0x0;
    McbspaRegs.MCR1.all=0x0;
    McbspaRegs.PCR1.all=0x0a00;
// Bit changes for the test  
 
    McbspaRegs.SPCR1.bit.RJUST =00;                     // word Rjustifed 
    McbspaRegs.SRGR2.bit.FSGM=1;                        // FSGM =1 for FSX based on write to DXR -XSR
                                                       // has to be set FWID to work!
    McbspaRegs.SRGR2.bit.FPER    =21;                       // set FPER = 21
    McbspaRegs.SRGR1.bit.CLKGDV  =03;                     // set CLKGDV = 3
    McbspaRegs.SRGR1.bit.FWID    =03;                       // set Fwidth =8      
    McbspaRegs.RCR2.bit.RCOMPAND =00;                   // No R/XCOMPAND 
    McbspaRegs.RCR2.bit.RDATDLY  =00;
    McbspaRegs.XCR2.bit.XCOMPAND =00;                     
    McbspaRegs.XCR2.bit.XDATDLY  =00;
    McbspaRegs.RCR1.bit.RWDLEN1  =3;                    // 16-bit word
    McbspaRegs.XCR1.bit.XWDLEN1  =3;                    // 16-bit word
    
 //  McBSP Reset to enable 
    McbspaRegs.SPCR2.bit.XRST =1;                       // enable XRST/RRST
    McbspaRegs.SPCR1.bit.RRST=1;
//    delay_loop(100);   
    McbspaRegs.SPCR2.all |=0x0040;                      // Only enable FRST,GRST used after 
    McbspaRegs.SPCR2.bit.FRST = 1;
}

void mcbsp_xmit(int a)
{  // while(McbspaRegs.SPCR2.bit.XRDY ==0) { }
	McbspaRegs.DXR2.all=0x7;
    McbspaRegs.DXR1.all=a;
    while(McbspaRegs.SPCR2.bit.XRDY ==0) { }           // Check for receive
    McbspaRegs.DXR2.all=0xF;
    McbspaRegs.DXR1.all=0xFFFF;
    while(McbspaRegs.SPCR2.bit.XRDY ==0) { }
} 

void SYNC_UP()
{
//	Toggle_M0(0);	         // Clear M0
	McbspaRegs.SPCR2.bit.FRST = 1;

	Toggle_Ms(0);	         // Clear M1
    Toggle_CS(0);            // Clear /CS
	mcbsp_xmit(0x8000);    
//	Toggle_Ms(1);	         // Set M1
	    while(McbspaRegs.SPCR1.bit.RRDY != 1) { }
// Wait for McBSP FIFO receive ready
	    AD_temp1 = McbspaRegs.DRR2.all;        // Receive Channel data and MSB
	    AD_temp0 = McbspaRegs.DRR1.all;        // Receive 15 LSB's
//	    while(McbspaRegs.MFFRX.bit.ST ==0) { }	    
//	Toggle_M0(1);	         // Set M0
//	Toggle_Ms(1);	         // Set M1
//delay_loop(100);
// Toggle_RD_CONVST via Frame Sync;        
//	while(McbspaRegs.SPCR1.bit.RRDY != 1) { }
// Wait for McBSP FIFO receive ready
//	    AD_temp1 = McbspaRegs.DRR2.all;        // Receive Channel data and MSB
//	    AD_temp0 = McbspaRegs.DRR1.all;        // Receive 15 LSB's 
	Toggle_Ms(1);	         // Set M1
	while(McbspaRegs.SPCR1.bit.RRDY != 1) { }
// Wait for McBSP FIFO receive ready
	    AD_temp1 = McbspaRegs.DRR2.all;        // Receive Channel data and MSB
	    AD_temp0 = McbspaRegs.DRR1.all;        // Receive 15 LSB's 
	while(McbspaRegs.SPCR1.bit.RRDY != 1) { }
// Wait for McBSP FIFO receive ready
	    AD_temp1 = McbspaRegs.DRR2.all;        // Receive Channel data and MSB
	    AD_temp0 = McbspaRegs.DRR1.all;        // Receive 15 LSB's 
	while(McbspaRegs.SPCR1.bit.RRDY != 1) { }
// Wait for McBSP FIFO receive ready
	    AD_temp1 = McbspaRegs.DRR2.all;        // Receive Channel data and MSB
	    AD_temp0 = McbspaRegs.DRR1.all;        // Receive 15 LSB's 

//	while(McbspaRegs.MFFRX.bit.ST==0) { }	    
//    Toggle_CS(1);            // Set /CS
//    McbspaRegs.SPCR2.bit.FRST = 0;    
}

void Toggle_CS(int state)
{
	switch(state)
	{
	case 0:
    	GpioDataRegs.GPECLEAR.all = 0x0001;  // Test Clear 
        break;    	   
	case 1:
    	GpioDataRegs.GPESET.all = 0x0001;    // Test Set
        break;
    }	
}

void Toggle_Ms(int state)
{
	switch(state)
	{
	case 0:
		GpioDataRegs.GPFCLEAR.all = 0x0005;  // Clear M1    
		break;
	case 1:
		GpioDataRegs.GPFSET.all = 0x0005;    // Set M1 High
		break;
	}
}

void Toggle_M1(int state)
{
	switch(state)
	{
	case 0:
		GpioDataRegs.GPFCLEAR.all = 0x0004;  // Clear M1    
		break;
	case 1:
		GpioDataRegs.GPFSET.all = 0x0004;    // Set M1 High
		break;
	}
}

void Toggle_M0(int state)
{
	switch(state)
	{
	case 0:
		GpioDataRegs.GPFCLEAR.all = 0x0001;  // Clear M0    
		break;
	case 1:
		GpioDataRegs.GPFSET.all = 0x0001;    // Set M0 High
		break;
	}
}

void Toggle_A0(int state)
{
	switch(state)
	{
	case 0:
    	GpioDataRegs.GPFCLEAR.all = 0x0002;   // Clear A0    
		break;
	case 1:
		GpioDataRegs.GPFSET.all = 0x0002;     // Set A0
		break;
	}
}

//===========================================================================
// End Program.
//===========================================================================