mpc107dma.c

VxWorks系统中DMA控制器驱动部分的源代码。

* RETURNS :
* This routine returns one of the following :
* MPC107_DMA_PERIODIC_CH_BUSY  or  MPC107_DMA_PERIODIC_CH_FREE or
* MPC107_DMA_CHAIN_CH_BUSY  or  MPC107_DMA_CHAIN_CH_FREE or
* MPC107_DMA_DIRECT_CH_BUSY  or   MPC107_DMA_CHAIN_CH_FREE or
* MPC107_DMA_UNDEF_CH
*/

INT32 mpc107DmaStatus
    (
    ULONG 	channel           /* Channel Number */
    )
    {
    ULONG 	dmaModeRegRead;   /* Data read from the DMA Mode register */
    UINT32 	dmaStatusReg;     /* DMA status Register */
    UINT32 	dmaModeReg;       /* DMA mode Register */

    if (channel == MPC107_DMA_CHANNEL0) /*  Channel 0 */
        {

        dmaStatusReg = (UINT32)MPC107_DMA_DSR0; /* Status Register of Ch0 */

        dmaModeReg = (UINT32)MPC107_DMA_DMR0;   /* Mode Register of Ch0 */

        }
    else if (channel == MPC107_DMA_CHANNEL1) /* Channel 1 */
        {

        dmaStatusReg = (UINT32)MPC107_DMA_DSR1; /* Status Register of Ch1 */

        dmaModeReg = (UINT32)MPC107_DMA_DMR1;    /* Mode Register of Ch1 */

        }
    else
        return (MPC107_DMA_UNDEF_CH); /* If the Channel is  undefined */



    dmaModeRegRead = MPC107EUMBBARREAD(dmaModeReg);


    /* if Chained DMA is configured */

    if ((dmaModeRegRead & MPC107_DMA_DMR_CTM) == 0 )
        {

        /* if Periodic  DMA is configured */

        if ((dmaModeRegRead & MPC107_DMA_DMR_PDE) != 0)
            {

            if ((MPC107EUMBBARREAD(dmaStatusReg) & MPC107_DMA_DSR_CB) != 0)
                {

                /*
                 * Periodic Chained DMA is configured
                 * and Channel Is Busy
                 */

                return (MPC107_DMA_PERIODIC_CH_BUSY);

                }
            else
                {

                /*
                 * Periodic Chained DMA is configured
                 * and Channel Is Not Busy (FREE)
                 */

                return (MPC107_DMA_PERIODIC_CH_FREE);
                }

            }

        else
            {

            if ((MPC107EUMBBARREAD(dmaStatusReg) & MPC107_DMA_DSR_CB) != 0)
                {

                /* Chained DMA is configured  and Channel Is Busy  */

                return (MPC107_DMA_CHAIN_CH_BUSY);

                }
            else
                {

                /*
                 * Chained DMA is configured and
                 * Channel Is Not Busy (FREE)
                 */

                return (MPC107_DMA_CHAIN_CH_FREE);
                }

            }

        }

        /* if Direct DMA is configured */

    else if ((dmaModeRegRead & MPC107_DMA_DMR_CTM) != 0)
        {

        if ((MPC107EUMBBARREAD(dmaStatusReg) & MPC107_DMA_DSR_CB) != 0)
            {

            /* Direct  DMA is configured  and Channel Is Busy  */

            return (MPC107_DMA_DIRECT_CH_BUSY);

            }
        else
            {

            /*
             * Direct  DMA is configured and
             * Channel Is Not Busy (FREE)
             */

            return (MPC107_DMA_DIRECT_CH_FREE);

            }

        }

    return (OK);

    }


/***************************************************************************
*
* mpc107DmaCh0Int -  ISR Handler for DMA channel 0
*
* This routine services the interrupts of DMA channel 0.
*
* RETURNS: N/A
*/

void mpc107DmaCh0Int (void)
    {
    MPC107_DMA_DESCRIPTOR *	pTempDescriptor;
    MPC107_DMA_DESCRIPTOR *	pTempFirstDescriptor;
    ULONG 		dataReadDmaReg;
    ULONG 		dataReadTemp;


    /* Read the status Register of DMA Channel 0 */

    dataReadDmaReg = MPC107EUMBBARREAD(MPC107_DMA_DSR0);


    /* if End of Chain / Direct Transfer Interrupt received */

    if ((dataReadDmaReg & MPC107_DMA_DSR_EOCAI) != 0)
        {

        dataReadTemp = MPC107EUMBBARREAD(MPC107_DMA_DMR0);

        /* if End of Interrupt Enabled */

        if ((dataReadTemp & MPC107_DMA_DMR_EOTIE) != 0)
            {

            if ((!(dataReadDmaReg & MPC107_DMA_DMR_CTM) &&
                  (dataReadDmaReg & MPC107_DMA_DMR_PDE)) != 0)
                {

                /* This channel is configured for Periodic DMA */



                }
            else if ( !(dataReadDmaReg & MPC107_DMA_DMR_CTM) &&
                      !(dmaBuildDescrInProgCh0))
                {

                /* This channel is configured for Chained DMA */


                /* Release all the Descriptors */

                pTempFirstDescriptor = pFirstDescriptorCh0;

                /* Descriptors Already Exist */

                if (((UINT32)pTempFirstDescriptor &
                     MPC107_DMA_NDAR_ADDR_MASK) != 0)
                    {


                    while (((UINT32)pTempFirstDescriptor  &
                            MPC107_DMA_NDAR_ADDR_MASK) != NULL )
                        {

                        pTempDescriptor = pTempFirstDescriptor;


                        pTempFirstDescriptor = pTempFirstDescriptor
                                             -> pNextDescriptorAddress;

                        free ((void *)((UINT32)pTempDescriptor &
                               MPC107_DMA_NDAR_ADDR_MASK));

                        }
                    }

                    pFirstDescriptorCh0 = NULL;

                    chainedDma0FirstTime = FALSE; /* Reset the flag */

                }

            }

        }


    /* if End of Segment Transfer Interrupt received */

    if ((dataReadDmaReg & MPC107_DMA_DSR_EOSI) != 0)
        {

        dataReadTemp = MPC107EUMBBARREAD(MPC107_DMA_CDAR0) &
                                         MPC107_DMA_CDAR_EOSIE;

        /* if End Of Segment Interrupt is Enabled  */

        if (dataReadTemp != 0)
            {

            }

        }


    /* If PCI Error  Interrupt received */

    if ((dataReadDmaReg & MPC107_DMA_DSR_PE) != 0)
        {

        dataReadTemp = MPC107EUMBBARREAD(MPC107_DMA_DMR0) &
                                         MPC107_DMA_DMR_EIE;

        /* If Error  Interrupts are  Enabled  */

        if (dataReadTemp != 0 )
            {

            }

        }


    /* If Local Memory Error   Interrupt received */

    if ((dataReadDmaReg & MPC107_DMA_DSR_LME) != 0)
        {

        dataReadTemp = MPC107EUMBBARREAD(MPC107_DMA_DMR0) &
                                         MPC107_DMA_DMR_EIE;

        /* If Error  Interrupts are  Enabled  */

        if (dataReadTemp != 0)
            {

            }

        }

    }


/***************************************************************************
*
* mpc107DmaCh1Int -  ISR Handler for DMA channel 1
*
* This routine services the interrupts of DMA channel 1.
*
* RETURNS: N/A
*/

void mpc107DmaCh1Int (void)
    {
    MPC107_DMA_DESCRIPTOR *	pTempDescriptor;
    MPC107_DMA_DESCRIPTOR *	pTempFirstDescriptor;
    ULONG 		dataReadDmaReg;
    ULONG 		dataReadTemp;

    /* Read the status Register of DMA Channel 1 */

    dataReadDmaReg = MPC107EUMBBARREAD(MPC107_DMA_DSR1);


    /* If End of Chain / Direct Transfer Interrupt received */

    if (dataReadDmaReg & MPC107_DMA_DSR_EOCAI)
        {

        dataReadTemp = MPC107EUMBBARREAD(MPC107_DMA_DMR1);

        /* If End of Interrupt Enabled */

        if ( dataReadTemp & MPC107_DMA_DMR_EOTIE )
            {

            if ( !( dataReadDmaReg & MPC107_DMA_DMR_CTM) &&
                  ( dataReadDmaReg & MPC107_DMA_DMR_PDE))
                {

                /* This channel is configured for Periodic DMA */


                }
            else if ( !( dataReadDmaReg & MPC107_DMA_DMR_CTM)  &&
                      !(dmaBuildDescrInProgCh1))
                {

                /* This channel is configured for Chained DMA */


                /* Release all the Descriptors */

                pTempFirstDescriptor = pFirstDescriptorCh1;

                /* Descriptors Already Exist */

                if (((UINT32)pTempFirstDescriptor & MPC107_DMA_NDAR_ADDR_MASK))
                    {


                    while (((UINT32)pTempFirstDescriptor  &
                            MPC107_DMA_NDAR_ADDR_MASK) != NULL )
                        {

                        pTempDescriptor = pTempFirstDescriptor;

                        pTempFirstDescriptor = pTempFirstDescriptor
                                        -> pNextDescriptorAddress;

                        free ((void *) ((UINT32)pTempDescriptor &
                                         MPC107_DMA_NDAR_ADDR_MASK));

                        }
                    }

                    pFirstDescriptorCh1 = NULL;

                    chainedDma1FirstTime = FALSE; /* Reset the flag */


                }


            }

        }


    /* If End of Segment Transfer Interrupt received */

    if (dataReadDmaReg & MPC107_DMA_DSR_EOSI)
        {

        dataReadTemp = MPC107EUMBBARREAD(MPC107_DMA_CDAR1) &
                                         MPC107_DMA_CDAR_EOSIE;

        /* If End Of Segment Interrupt is Enabled  */

        if (dataReadTemp)
            {

            }

        }


    /* If PCI Error  Interrupt received */

    if (dataReadDmaReg & MPC107_DMA_DSR_PE)
        {

        dataReadTemp = MPC107EUMBBARREAD(MPC107_DMA_DMR1) &
                                         MPC107_DMA_DMR_EIE;

        /* If Error  Interrupts are  Enabled  */

        if (dataReadTemp)
            {

            }

        }


    /* If Local Memory Error   Interrupt received */

    if (dataReadDmaReg & MPC107_DMA_DSR_LME)
        {

        dataReadTemp = MPC107EUMBBARREAD(MPC107_DMA_DMR1) &
                                         MPC107_DMA_DMR_EIE;

        /* If Error  Interrupts are  Enabled  */

        if (dataReadTemp)
            {

            }

        }

    }