l64853dma.c

VxWorks系统中DMA控制器驱动部分的源代码。

void l64853DmaEnable
    (
    L64853 *pL64853          /* ptr to an L64853 structure */
    )
    {
    L64853_CSR_BIT_SET (pL64853, L64853_CSR_EN_DMA);
    }

/*******************************************************************************
*
* l64853DmaDisable - prevent the L64853 DMA chip from accepting DMA requests
* 
* This routine disables acceptance of DMA requests from a D channel device by
* the L64853 DMA controller, by resetting the enable DMA bit
* (L64853_CSR_EN_DMA) in the CSR register.
*
* RETURNS: N/A
*
* SEE ALSO: l64853DmaEnable()
*/

void l64853DmaDisable
    (
    L64853 *pL64853          /* ptr to an L64853 structure */
    )
    {
    L64853_CSR_BIT_RESET (pL64853, L64853_CSR_EN_DMA);
    }

/*******************************************************************************
*
* l64853CountEnable - enable the byte counter of the L64853 DMA controller
* 
* This routine enables the byte counter of the L64853 DMA controller, by
* setting the enable counter bit (L64853_CSR_EN_CNT) in the CSR register.  The
* byte counter holds the number of bytes remaining in the current D channel
* DMA transfer.
*
* RETURNS: N/A
*
* SEE ALSO: l64853CountDisable(), l64853TermCountTest()
*/

void l64853CountEnable
    (
    L64853 *pL64853          /* ptr to an L64853 structure */
    )
    {
    L64853_CSR_BIT_SET (pL64853, L64853_CSR_EN_CNT);
    }

/*******************************************************************************
*
* l64853CountDisable - disable the byte counter of the L64853 DMA controller
* 
* This routine disables the byte counter of the L64853 DMA controller, by
* resetting the enable counter bit (L64853_CSR_EN_CNT) in the CSR register.
*
* RETURNS: N/A
*
* SEE ALSO: l64853CountEnable()
*/

void l64853CountDisable
    (
    L64853 *pL64853          /* ptr to an L64853 structure */
    )
    {
    L64853_CSR_BIT_RESET (pL64853, L64853_CSR_EN_CNT);
    }

/*******************************************************************************
*
* l64853ErrPendTest - test the L64853 DMA controller for an error
*
* This routine determines whether the error pending bit (L64853_CSR_ERR_PEND)
* of the L64853 CSR register is set.
*
* RETURNS : TRUE if there is a DMA error, otherwise FALSE.
*/

BOOL l64853ErrPendTest
    (
    L64853 *pL64853          /* ptr to an L64853 structure */
    )
    {
    return ((*pL64853->pCsrReg & L64853_CSR_ERR_PEND) ? TRUE : FALSE);
    }

/*******************************************************************************
*
* l64853PackCountGet - get the L64853 DMA controller pack count
*
* This routine returns the number of bytes in the D channel pack register of
* the L64853 DMA controller.
*
* RETURNS : An integer value of the pack count bits (L64853_CSR_PACK_CNT) of
* the CSR register.
*/

int l64853PackCountGet
    (
    L64853 *pL64853          /* ptr to an L64853 structure */
    )
    {
    return ((*pL64853->pCsrReg & L64853_CSR_PACK_CNT) >> 2);
    }

/*******************************************************************************
*
* l64853ReqPendTest - test the L64853 DMA controller for a DMA transfer
*
* This routine determines whether the request pending bit
* (L64853_CSR_REQ_PEND) of the L64853 CSR register is set.  This bit is set
* when a D channel DMA transfer is in progress.
*
* RETURNS : TRUE if there is an active DMA transfer, otherwise FALSE.
*/

BOOL l64853ReqPendTest
    (
    L64853 *pL64853          /* ptr to an L64853 structure */
    )
    {
    return ((*pL64853->pCsrReg & L64853_CSR_REQ_PEND) ? TRUE : FALSE);
    }

/*******************************************************************************
*
* l64853ByteAdrsGet - get the byte address bits of the L64853 CSR register
*
* This routine returns the byte address bits (L64853_CSR_BYTE_ADDR) of the
* L64853 CSR register.  These are the two least significant bits of the
* address of the next byte to be accessed by the D channel controller.
*
* RETURNS : The integer value of the byte address bits.
*/

int l64853ByteAdrsGet
    (
    L64853 *pL64853          /* ptr to an L64853 structure */
    )
    {
    return ((*pL64853->pCsrReg & L64853_CSR_BYTE_ADDR) >> 11);
    }

/*******************************************************************************
*
* l64853TermCountTest - test the L64853 DMA chip for an expired byte counter
*
* This routine determines whether the byte counter has expired by testing the
* terminal count bit (L64853_CSR_TC) of the L64853 CSR register.
*
* RETURNS : TRUE if the terminal count bit is set, otherwise FALSE.
*/

BOOL l64853TermCountTest
    (
    L64853 *pL64853          /* ptr to an L64853 structure */
    )
    {
    return ((*pL64853->pCsrReg & L64853_CSR_TC) ? TRUE : FALSE);
    }

/*******************************************************************************
*
* l64853DevIdGet - get the device ID bits of the L64853 CSR register
*
* This routine returns the device ID bits (L64853_CSR_DEV_ID) of the L64853
* CSR register.
*
* RETURNS : The integer value of the device ID bits.
*/


int l64853DevIdGet
    (
    L64853 *pL64853          /* ptr to an L64853 structure */
    )
    {
    return ((*pL64853->pCsrReg & L64853_CSR_DEV_ID) >> 28);
    }

/*******************************************************************************
*
* l64853AdrsCountGet - get the SBus address in the L64853 DMA address counter
*
* This routine returns the contents of the L64853 DMA address counter. This
* register contains the virtual address of the SBus memory for a D channel DMA
* transfer (read or write).
*
* RETURNS : The current virtual address in the address counter.
*
* SEE ALSO: l64853AdrsCountSet()
*/

char * l64853AdrsCountGet
    (
    L64853 *pL64853          /* ptr to an L64853 structure */
    )
    {
    return ((char *) *pL64853->pAdrsReg);
    }

/*******************************************************************************
*
* l64853AdrsCountSet - set the starting address for a D channel DMA transfer
*
* This routine writes a specified SBus address to the L64853 DMA address
* counter.  This address is used as the starting virtual address for a D
* channel DMA transfer (read or write).
*
* RETURNS: N/A
*
* SEE ALSO: l64853AdrsCountGet()
*/

void l64853AdrsCountSet
    (
    L64853 *pL64853,         /* ptr to an L64853 structure */
    char *pAdrsCount            /* ptr */
    )
    {
    *pL64853->pAdrsReg = (UINT32) pAdrsCount;
    }

/*******************************************************************************
*
* l64853ByteCountGet - get the contents of the L64853 DMA byte counter
*
* This routine returns the number of bytes remaining in the current D channel
* DMA transfer.
*
* RETURNS : The contents of the DMA byte counter.
*
* SEE ALSO: l64853ByteCountSet()
*/

int l64853ByteCountGet
    (
    L64853 *pL64853          /* ptr to an L64853 structure */
    )
    {
    return ((int) *pL64853->pBcntReg);
    }

/*******************************************************************************
*
* l64853ByteCountSet - set the size of a D channel DMA transfer
*
* This routine sets the size the D channel DMA transfer by loading the value,
* <byteCount>, into the L64853 DMA byte counter.
*
* RETURNS: N/A
* 
* SEE ALSO: l64853ByteCountGet()
*/

void l64853ByteCountSet
    (
    L64853 *pL64853,         /* ptr to an L64853 structure */
    int byteCount               /* ptr */
    )
    {
    *pL64853->pBcntReg = (UINT32) byteCount;
    }

/*******************************************************************************
*
* l64853HwInit - initialize the L64853 DMA controller to a quiescent state
*
* This routine resets the L64853 DMA chip, and clears the interrupt enable,
* DMA enable, and counter enable bits in the CSR register, putting the DMA
* controller in a quiescent state.
*
* RETURNS: N/A
*
* SEE ALSO: l64853Reset()
*/

LOCAL void l64853HwInit
    (
    L64853 *pL64853          /* ptr to an L64853 structure */
    )
    {
    l64853Reset (pL64853);

    /* clear various enable bits */

    L64853_CSR_BIT_RESET (pL64853, L64853_CSR_INT_EN);
    L64853_CSR_BIT_RESET (pL64853, L64853_CSR_EN_DMA);
    L64853_CSR_BIT_RESET (pL64853, L64853_CSR_EN_CNT);
    }

/*******************************************************************************
*
* l64853Show - display the contents of all readable L64853 DMA chip registers
*
* This routine displays the state of the L64853 DMA controller, by printing
* the contents of all readable registers.  It is used only during debugging.
*
* RETURNS: OK, or ERROR if both the parameter <pDmaCtrl> and the global
* variable <pSysDmaCtrl> are NULL.
*
* SEE ALSO: sysDmaShow()
*/

STATUS l64853Show
    (
    FAST DMA_CTRL *pDmaCtrl     /* ptr to DMA controller info */
    )
    {
    FAST UINT32 csrRegCopy;
    FAST L64853_DMA_CTRL *pl64853DmaCtrl;	/* ptr to L64853 info */

    if (pDmaCtrl == NULL)
        {
        if (pSysDmaCtrl != NULL)
            pDmaCtrl = pSysDmaCtrl;
        else
            {
            printErr ("No DMA controller specified.\n");
            return (ERROR);
            }
        }

    pl64853DmaCtrl = (L64853_DMA_CTRL *) pDmaCtrl;

    csrRegCopy = *pl64853DmaCtrl->pCsrReg;

    printf ("Interrupt Pending:   %s\n",
	    (csrRegCopy & L64853_CSR_INT_PEND) 	? " SET " : "reset");
    printf ("Error Pending:       %s\n",
	    (csrRegCopy & L64853_CSR_ERR_PEND) 	? " SET " : "reset");
    printf ("Interrupt Enable:    %s\n",
	    (csrRegCopy & L64853_CSR_INT_EN) 	? " SET " : "reset");
    printf ("Drain Buffer:        %s\n",
	    (csrRegCopy & L64853_CSR_DRAIN) 	? " SET " : "reset");
    printf ("Reset DMA:           %s\n",
	    (csrRegCopy & L64853_CSR_RESET) 	? " SET " : "reset");
    printf ("Write:               %s\n",
	    (csrRegCopy & L64853_CSR_WRITE) 	? " SET " : "reset");
    printf ("Enable DMA:          %s\n",
	    (csrRegCopy & L64853_CSR_EN_DMA) 	? " SET " : "reset");
    printf ("Request Pending:     %s\n",
	    (csrRegCopy & L64853_CSR_REQ_PEND) 	? " SET " : "reset");
    printf ("Enable Counter:      %s\n",
	    (csrRegCopy & L64853_CSR_EN_CNT) 	? " SET " : "reset");
    printf ("Terminal Count:      %s\n",
	    (csrRegCopy & L64853_CSR_TC) 	? " SET " : "reset");
    printf ("ILACC 79C900:        %s\n",
	    (csrRegCopy & L64853_CSR_ILACC) 	? " SET " : "reset");

    printf ("\n");

    printf ("Pack Count:        %d\n",
	    (csrRegCopy & L64853_CSR_PACK_CNT) >> 2);
    printf ("Byte Address:      %d\n",
	    (csrRegCopy & L64853_CSR_BYTE_ADDR) >> 11);
    printf ("Device ID:         %d\n",
	    (csrRegCopy & L64853_CSR_DEV_ID) >> 28);

    printf ("\n");

    printf ("DMA Address    Reg = 0x%08x\n", *pl64853DmaCtrl->pAdrsReg);
    printf ("DMA Byte Count Reg = 0x%08x\n", *pl64853DmaCtrl->pBcntReg);

    return (OK);
    }