l64853dma.c

VxWorks系统中DMA控制器驱动部分的源代码。

/* l64853Dma.c - LSI Logic L64853 S-Bus DMA Controller library */

/* Copyright 1989-1997 Wind River Systems, Inc. */
#include "copyright_wrs.h"

/*
modification history
--------------------
01f,29nov96,wlf  doc: cleanup.
01h,01jul96,map  added documentation.
01g,25may96,dat  added #include "stdio.h", to eliminate warnings
01f,25may96,dds  (from jaideep) modified l64853{HwInit,Reset} to do a
                 complete job ...
01f,23may96,wlf  doc: cleanup.
01e,03dec93,ccc  fixed warning by adding include of stdlib.h.
01d,02sep92,ccc  renamed l64853Lib.c to l64853Dma.c.
01c,26may92,rrr  the tree shuffle
		  -changed includes to have absolute path from h/
01b,04oct91,rrr  passed through the ansification filter
                  -changed functions to ansi style
		  -changed includes to have absolute path from h/
		  -changed VOID to void
		  -changed copyright notice
01a,28feb90,jcc  written
*/

/*
DESCRIPTION

This is the driver for the LSI Logic L64853 S-Bus DMA Controller. The device
supports two DMA channels; an 8-bit D channel and a 16-bit E channel.  The two
channels can be used for DMA or programmed IO and using the controller as an
SBus master or a slave. As an SBus master, the L64853 DMA controller, is
capable of operating as a DVMA master, generating virtual memory addresses on
the SBUS which are translated to physical addresses by the MMU on the SBus
controller.

Only D channel DMA operations is supported by this driver.  These DMA
operation are controlled through L64853 internal programmable registers, while
the E channel DMA operations are programmed through external registers located
on an E channel device.

The l64853 DMA controller uses the pack/unpack registers to buffer data.

USAGE

The routine l64853CtrlCreate() is called to create a DMA_CTRL structure which
is used to describe the L64853 controller. The routine l64853CtrlInit() is
used to initialize the chip before any operations are attempted on the L64853
controller by calling l64853HwInit().

The steps to setup a D channel DMA operation are,
.iP
Set the virtual memory address by calling l64853AdrCountSet().
.iP
Set the number of bytes to transfer by calling l64853ByteCountSet().
.iP
Set the direction transfer by calling l64853Read(), to perform DMA from
memory, or l64853Write() to perform DMA into memory.
.iP
Program the D channel device to request a DMA transfer causing an assertion
of the D_REQ line.
.iP
Enable the DMA by calling l64853DmaEnable(). DMA will now begin, and continue
until the byte count expires or if there is an error. If interrupts were
enabled by calling l64853IntEnable(), an interrupt is generated.
.iP
Service the interrupt, and if the completed DMA operation was a write to
memory, bytes pending in the pack register should be drained into memory by
calling l64853Drain(), otherwise the bytes should be flushed by calling
l64853Flush().
.LP

INCLUDE FILES
l64853.h

SEE ALSO:
.pG "I/O System"
*/

#include "vxWorks.h"
#include "drv/dma/l64853.h"
#include "memLib.h"
#include "stdlib.h"
#include "stdio.h"

/* defines */

#define WD_33C93_MAX_BYTES_PER_XFER  ((UINT) 0xffffff)

/* macros */

/*******************************************************************************
*
* L64853_CSR_BIT_SET - set the specified bit(s) in the L64853 CSR register
*
* NOMANUAL
*/

#define L64853_CSR_BIT_SET(pL64853, bit)		\
    do							\
	{						\
    	*pL64853->pCsrReg |= bit;			\
	} while (FALSE)

/*******************************************************************************
*
* L64853_CSR_BIT_RESET - reset the specified bit(s) in the L64853 CSR register
*
* NOMANUAL
*/

#define L64853_CSR_BIT_RESET(pL64853, bit)		\
    do							\
	{						\
        *pL64853->pCsrReg &= ~bit;			\
	} while (FALSE)

/* externals */

IMPORT DMA_CTRL *pSysDmaCtrl;


/* forward static functions */

static void l64853HwInit (L64853 *pL64853);


/*******************************************************************************
*
* l64853CtrlCreate - create an L64853 structure and initialize parts
*
* This routine creates an L64853 data structure.  It must be called before
* using an L64853 chip and should be called only once for a specified
* structure.  Since this routine allocates memory for a structure used by all
* routines in l64853Lib, it must be called before any other routines in the
* library.
*
* After calling this routine, at least one call to l64853CtrlInit() should
* be made before initiating any DMA transaction using the L64853.
*
* The input parameters are as follows:
* .iP <baseAdrs> 10
* the address where the CPU accesses the lowest (CSR) register of
* the L64853.
* .iP <regOffset> 10
* the address offset (in bytes) to access consecutive registers.
* .iP <pIdReg> 10
* the address where the CPU accesses the internal ID register.
* .LP
*
* RETURNS: A pointer to the L64853 control structure,
* or NULL if memory is unavailable or the parameters are invalid.
*
* SEE ALSO: l64853CtrlInit()
*/

DMA_CTRL *l64853CtrlCreate
    (
    UINT32 *    baseAdrs,       /* base address of the L64853 */
    int         regOffset,      /* address offset between consecutive regs. */
    UINT32 *    pIdReg          /* address of internal ID register */
    )
    {
    FAST L64853 *pL64853;		/* ptr to L64853 info */

    /* verify input parameters */

    if (regOffset == 0)
        return ((DMA_CTRL *) NULL);

    /* calloc the controller info structure; return NULL if unable */

    if ((pL64853 = (L64853 *) calloc (1, sizeof (L64853))) == NULL)
        return ((DMA_CTRL *) NULL);

    /* fill in L64853 specific data for this controller */

    pL64853->pCsrReg	= baseAdrs;
    pL64853->pAdrsReg	= (UINT32*) ((int) baseAdrs + (int) regOffset);
    pL64853->pBcntReg	= (UINT32*) ((int) baseAdrs + (0x2 * (int) regOffset));

    return ((DMA_CTRL *) pL64853);
    }

/*******************************************************************************
*
* l64853CtrlInit - initialize the L64853 hardware
*
* This routine initializes the L64853 hardware.  It should be called after
* l64853CtrlCreate(), but before the chip is actually used.
*
* The <pL64853> parameter is a pointer to the L64853_DMA_CTRL structure 
* created with l64853CtrlCreate().
*
* RETURNS: OK, always.
* 
* SEE ALSO: l64853CtrlCreate(), l64853HwInit()
*/

STATUS l64853CtrlInit
    (
    FAST L64853 *pL64853                /* ptr to L64853 info */
    )
    {
    l64853HwInit (pL64853); 	/* initialize the L64853 hardware */

    return (OK);
    }

/*******************************************************************************
*
* l64853IntEnable - enable L64853 DMA controller interrupts
*
* This routine allows the L64853 DMA controller to generate interrupts
* by setting the interrupt enable bit in the L64853 CSR register.
* The chip generates interrupts when an error is pending (CSR
* register bit L64853_CSR_ERR_PEND) or when the byte counter has expired (CSR
* register bit L64853_CSR_TC).  It also passes through interrupts from the D
* channel device.
*
* RETURNS: N/A
*
* SEE ALSO: l64853IntDisable()
*/

void l64853IntEnable
    (
    L64853 *pL64853          /* ptr to an L64853 structure */
    )
    {
    L64853_CSR_BIT_SET (pL64853, L64853_CSR_INT_EN);
    }

/*******************************************************************************
*
* l64853IntDisable - disable L64853 DMA controller interrupts
*
* This routine prevents the L64853 DMA controller from generating or 
* passing through interrupts by resetting the interrupt enable bit in 
* the L64853 CSR register.
*
* RETURNS: N/A
*
* SEE ALSO: l64853IntEnable()
*/

void l64853IntDisable
    (
    L64853 *pL64853          /* ptr to an L64853 structure */
    )
    {
    L64853_CSR_BIT_RESET (pL64853, L64853_CSR_INT_EN);
    }

/*******************************************************************************
*
* l64853Flush - flush the L64853 D channel pack register
*
* This routine sets the flush buffer bit in the CSR register of the L64853 DMA
* controller, clearing the pack count (CSR register bits L64853_CSR_PACK_CNT), 
* any pending errors (CSR register bit L64853_CSR_ERR_PEND), and the terminal
* count bit (CSR register bit L64853_CSR_TC).
*
* RETURNS: N/A
*/

void l64853Flush
    (
    L64853 *pL64853          /* ptr to an L64853 structure */
    )
    {
    L64853_CSR_BIT_SET (pL64853, L64853_CSR_FLUSH);
    }

/*******************************************************************************
*
* l64853Drain - drain the L64853 D channel pack register
*
* This routine sets the drain buffer bit in the CSR register of the L64853 DMA
* controller, causing any bytes in the D channel pack register to be written
* out to SBus memory; then it clears the pack count (CSR register bits
* L64853_CSR_PACK_CNT).
*
* RETURNS: N/A
*/

void l64853Drain
    (
    L64853 *pL64853          /* ptr to an L64853 structure */
    )
    {
    L64853_CSR_BIT_SET (pL64853, L64853_CSR_DRAIN);
    }

/*******************************************************************************
*
* l64853Reset - reset the L64853 DMA controller
*
* This routine toggles the reset bit in the CSR register of the L64853 DMA 
* controller, putting the DMA controller into the default initial state.
*
* RETURNS: N/A
*/

void l64853Reset
    (
    L64853 *pL64853          /* ptr to an L64853 structure */
    )
    {
    /* toggle reset bit to hardware reset the L64853 */
    
    L64853_CSR_BIT_SET   (pL64853, L64853_CSR_RESET);
    L64853_CSR_BIT_RESET (pL64853, L64853_CSR_RESET);
    }

/*******************************************************************************
*
* l64853Write - enable DMA transfers from a D channel device to SBus memory
*
* This routine permits the L64853 DMA controller to write data from a D
* channel device to SBus memory, by setting the write bit (L64853_CSR_WRITE)
* of the CSR register.
*
* RETURNS: N/A
* 
* SEE ALSO: l64853Read()
*/

void l64853Write
    (
    L64853 *pL64853          /* ptr to an L64853 structure */
    )
    {
    L64853_CSR_BIT_SET (pL64853, L64853_CSR_WRITE);
    }

/*******************************************************************************
*
* l64853Read - enable DMA transfers to a D channel device from SBus memory
* 
* This routine permits the L64853 DMA controller to read data from SBus memory
* into a D channel device, by clearing the write bit (L64853_CSR_WRITE) of the
* CSR register.
*
* RETURNS: N/A
*
* SEE ALSO: l64853Write()
*/

void l64853Read
    (
    L64853 *pL64853          /* ptr to an L64853 structure */
    )
    {
    L64853_CSR_BIT_RESET (pL64853, L64853_CSR_WRITE);
    }

/*******************************************************************************
*
* l64853DmaEnable - enable the L64853 DMA controller to accept DMA requests
* 
* This routine enables the L64853 DMA controller to accept DMA requests from a
* D channel device, by setting the enable DMA bit (L64853_CSR_EN_DMA) in the
* CSR register.
*
* RETURNS: N/A
*
* SEE ALSO: l64853DmaDisable()
*/