📄 trprtstp_1.c
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/*********************************************************************
* Filename: TRPRTSTP.c
*
* Description: This program illustrates the programmable transmit-priority
* and time stamping feature of the CAN module.
*
* When a priority is assigned, transmission will be according to the
* assigned transmit priority, not the numerical value of the mailbox ID.
* All mailboxes are configured for transmit operation and all TRS.n bits
* are set at the same time. Transmit priority is assigned randomly.
* The received data may be monitored on the CANalyzer to check if data was
* transmitted according to the assigned priority. The MOTS registers may
* also be checked on the transmitting node.
*
* Last update: 12/24/2002
*********************************************************************/
#include "DSP281x_Device.h" // DSP281x Headerfile Include File
#include "DSP281x_Examples.h" // DSP281x Examples Include File
Uint32 i;
main()
{
/* Create a shadow register structure for the CAN control registers. This is
needed, since, only 32-bit access is allowed to these registers. 16-bit access
to these registers could potentially corrupt the register contents. This is
especially true while writing to a bit (or group of bits) among bits 16 - 31 */
struct ECAN_REGS ECanaShadow;
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the DSP281x_SysCtrl.c file.
InitSysCtrl();
// Step 2. Initalize GPIO:
// This example function is found in the DSP281x_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
// InitGpio(); // Skipped for this example
// For this example, configure CAN pins using GPIO regs here
EALLOW;
GpioMuxRegs.GPFMUX.bit.CANTXA_GPIOF6 = 1;
GpioMuxRegs.GPFMUX.bit.CANRXA_GPIOF7 = 1;
EDIS;
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
DINT;
// Initialize PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the DSP281x_PieCtrl.c file.
InitPieCtrl();
// Disable CPU interrupts and clear all CPU interrupt flags:
IER = 0x0000;
IFR = 0x0000;
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example. This is useful for debug purposes.
// The shell ISR routines are found in DSP281x_DefaultIsr.c.
// This function is found in DSP281x_PieVect.c.
InitPieVectTable();
// Step 4. Initialize all the Device Peripherals:
// This function is found in DSP281x_InitPeripherals.c
// InitPeripherals(); // Not required for this example
// Step 5. User specific code, enable interrupts:
// eCAN control registers require 32-bit access.
// If you want to write to a single bit, the compiler may break this
// access into a 16-bit access. One solution, that is presented here,
// is to use a shadow register to force the 32-bit access.
// Read the entire register into a shadow register. This access
// will be 32-bits. Change the desired bit and copy the value back
// to the eCAN register with a 32-bit write.
// Configure the eCAN RX and TX pins for eCAN transmissions
EALLOW;
ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all;
ECanaShadow.CANTIOC.bit.TXFUNC = 1;
ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all;
ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all;
ECanaShadow.CANRIOC.bit.RXFUNC = 1;
ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all;
EDIS;
// Disable all Mailboxes
// Since this write is to the entire register (instead of a bit
// field) a shadow register is not required.
/* Write to the MSGID field of TRANSMIT mailboxes MBOX0 - 31 */
ECanaMboxes.MBOX0.MSGID.all = 0x9555AA00;
ECanaMboxes.MBOX1.MSGID.all = 0x9555AA01;
ECanaMboxes.MBOX2.MSGID.all = 0x9555AA02;
ECanaMboxes.MBOX3.MSGID.all = 0x9555AA03;
ECanaMboxes.MBOX4.MSGID.all = 0x9555AA04;
ECanaMboxes.MBOX5.MSGID.all = 0x9555AA05;
ECanaMboxes.MBOX6.MSGID.all = 0x9555AA06;
ECanaMboxes.MBOX7.MSGID.all = 0x9555AA07;
ECanaMboxes.MBOX8.MSGID.all = 0x9555AA08;
ECanaMboxes.MBOX9.MSGID.all = 0x9555AA09;
ECanaMboxes.MBOX10.MSGID.all = 0x9555AA10;
ECanaMboxes.MBOX11.MSGID.all = 0x9555AA11;
ECanaMboxes.MBOX12.MSGID.all = 0x9555AA12;
ECanaMboxes.MBOX13.MSGID.all = 0x9555AA13;
ECanaMboxes.MBOX14.MSGID.all = 0x9555AA14;
ECanaMboxes.MBOX15.MSGID.all = 0x9555AA15;
ECanaMboxes.MBOX16.MSGID.all = 0x9555AA16;
ECanaMboxes.MBOX17.MSGID.all = 0x9555AA17;
ECanaMboxes.MBOX18.MSGID.all = 0x9555AA18;
ECanaMboxes.MBOX19.MSGID.all = 0x9555AA19;
ECanaMboxes.MBOX20.MSGID.all = 0x9555AA20;
ECanaMboxes.MBOX21.MSGID.all = 0x9555AA21;
ECanaMboxes.MBOX22.MSGID.all = 0x9555AA22;
ECanaMboxes.MBOX23.MSGID.all = 0x9555AA23;
ECanaMboxes.MBOX24.MSGID.all = 0x9555AA24;
ECanaMboxes.MBOX25.MSGID.all = 0x9555AA25;
ECanaMboxes.MBOX26.MSGID.all = 0x9555AA26;
ECanaMboxes.MBOX27.MSGID.all = 0x9555AA27;
ECanaMboxes.MBOX28.MSGID.all = 0x9555AA28;
ECanaMboxes.MBOX29.MSGID.all = 0x9555AA29;
ECanaMboxes.MBOX30.MSGID.all = 0x9555AA30;
ECanaMboxes.MBOX31.MSGID.all = 0x9555AA31;
/* Configure Mailboxes 0-31 as Tx */
ECanaRegs.CANMD.all = 0x00000000;
/* Enable all Mailboxes */
ECanaRegs.CANME.all = 0xFFFFFFFF;
/* Write to Master Control field - DLC */
ECanaMboxes.MBOX0.MSGCTRL.bit.DLC = 8;
ECanaMboxes.MBOX1.MSGCTRL.bit.DLC = 8;
ECanaMboxes.MBOX2.MSGCTRL.bit.DLC = 8;
ECanaMboxes.MBOX3.MSGCTRL.bit.DLC = 8;
ECanaMboxes.MBOX4.MSGCTRL.bit.DLC = 8;
ECanaMboxes.MBOX5.MSGCTRL.bit.DLC = 8;
ECanaMboxes.MBOX6.MSGCTRL.bit.DLC = 8;
ECanaMboxes.MBOX7.MSGCTRL.bit.DLC = 8;
ECanaMboxes.MBOX8.MSGCTRL.bit.DLC = 8;
ECanaMboxes.MBOX9.MSGCTRL.bit.DLC = 8;
ECanaMboxes.MBOX10.MSGCTRL.bit.DLC = 8;
ECanaMboxes.MBOX11.MSGCTRL.bit.DLC = 8;
ECanaMboxes.MBOX12.MSGCTRL.bit.DLC = 8;
ECanaMboxes.MBOX13.MSGCTRL.bit.DLC = 8;
ECanaMboxes.MBOX14.MSGCTRL.bit.DLC = 8;
ECanaMboxes.MBOX15.MSGCTRL.bit.DLC = 8;
ECanaMboxes.MBOX16.MSGCTRL.bit.DLC = 8;
ECanaMboxes.MBOX17.MSGCTRL.bit.DLC = 8;
ECanaMboxes.MBOX18.MSGCTRL.bit.DLC = 8;
ECanaMboxes.MBOX19.MSGCTRL.bit.DLC = 8;
ECanaMboxes.MBOX20.MSGCTRL.bit.DLC = 8;
ECanaMboxes.MBOX21.MSGCTRL.bit.DLC = 8;
ECanaMboxes.MBOX22.MSGCTRL.bit.DLC = 8;
ECanaMboxes.MBOX23.MSGCTRL.bit.DLC = 8;
ECanaMboxes.MBOX24.MSGCTRL.bit.DLC = 8;
ECanaMboxes.MBOX25.MSGCTRL.bit.DLC = 8;
ECanaMboxes.MBOX26.MSGCTRL.bit.DLC = 8;
ECanaMboxes.MBOX27.MSGCTRL.bit.DLC = 8;
ECanaMboxes.MBOX28.MSGCTRL.bit.DLC = 8;
ECanaMboxes.MBOX29.MSGCTRL.bit.DLC = 8;
ECanaMboxes.MBOX30.MSGCTRL.bit.DLC = 8;
ECanaMboxes.MBOX31.MSGCTRL.bit.DLC = 8;
/* Set transmit priority level - Random priorities are assigned
Uncomment following block to check out the TPL mechanism */
ECanaMboxes.MBOX20.MSGCTRL.bit.TPL = 31;
ECanaMboxes.MBOX4.MSGCTRL.bit.TPL = 30;
ECanaMboxes.MBOX9.MSGCTRL.bit.TPL = 29;
ECanaMboxes.MBOX26.MSGCTRL.bit.TPL = 28;
ECanaMboxes.MBOX15.MSGCTRL.bit.TPL = 27;
ECanaMboxes.MBOX0.MSGCTRL.bit.TPL = 26;
ECanaMboxes.MBOX7.MSGCTRL.bit.TPL = 25;
ECanaMboxes.MBOX23.MSGCTRL.bit.TPL = 24;
ECanaMboxes.MBOX11.MSGCTRL.bit.TPL = 23;
ECanaMboxes.MBOX17.MSGCTRL.bit.TPL = 22;
ECanaMboxes.MBOX27.MSGCTRL.bit.TPL = 21;
ECanaMboxes.MBOX13.MSGCTRL.bit.TPL = 20;
ECanaMboxes.MBOX18.MSGCTRL.bit.TPL = 19;
ECanaMboxes.MBOX2.MSGCTRL.bit.TPL = 18;
ECanaMboxes.MBOX24.MSGCTRL.bit.TPL = 17;
ECanaMboxes.MBOX29.MSGCTRL.bit.TPL = 16;
ECanaMboxes.MBOX12.MSGCTRL.bit.TPL = 15;
ECanaMboxes.MBOX16.MSGCTRL.bit.TPL = 14;
ECanaMboxes.MBOX31.MSGCTRL.bit.TPL = 13;
ECanaMboxes.MBOX22.MSGCTRL.bit.TPL = 12;
ECanaMboxes.MBOX19.MSGCTRL.bit.TPL = 11;
ECanaMboxes.MBOX21.MSGCTRL.bit.TPL = 10;
ECanaMboxes.MBOX1.MSGCTRL.bit.TPL = 9;
ECanaMboxes.MBOX30.MSGCTRL.bit.TPL = 8;
ECanaMboxes.MBOX28.MSGCTRL.bit.TPL = 7;
ECanaMboxes.MBOX25.MSGCTRL.bit.TPL = 6;
ECanaMboxes.MBOX10.MSGCTRL.bit.TPL = 5;
ECanaMboxes.MBOX3.MSGCTRL.bit.TPL = 4;
ECanaMboxes.MBOX8.MSGCTRL.bit.TPL = 3;
ECanaMboxes.MBOX5.MSGCTRL.bit.TPL = 2;
ECanaMboxes.MBOX14.MSGCTRL.bit.TPL = 1;
ECanaMboxes.MBOX6.MSGCTRL.bit.TPL = 0;
/* If no tr.priority is assigned, tr.sequence will be starting
with the mailbox with the highest priority, which will be the
mailbox with the numerically highest ID. 31,30,29.........2,1,0
Uncomment the following block to try this out */
/*ECanaMboxes.MBOX20.MSGCTRL.bit.TPL = 0;
ECanaMboxes.MBOX4.MSGCTRL.bit.TPL = 0;
ECanaMboxes.MBOX9.MSGCTRL.bit.TPL = 0;
ECanaMboxes.MBOX26.MSGCTRL.bit.TPL = 0;
ECanaMboxes.MBOX15.MSGCTRL.bit.TPL = 0;
ECanaMboxes.MBOX0.MSGCTRL.bit.TPL = 0;
ECanaMboxes.MBOX7.MSGCTRL.bit.TPL = 0;
ECanaMboxes.MBOX23.MSGCTRL.bit.TPL = 0;
ECanaMboxes.MBOX11.MSGCTRL.bit.TPL = 0;
ECanaMboxes.MBOX17.MSGCTRL.bit.TPL = 0;
ECanaMboxes.MBOX27.MSGCTRL.bit.TPL = 0;
ECanaMboxes.MBOX13.MSGCTRL.bit.TPL = 0;
ECanaMboxes.MBOX18.MSGCTRL.bit.TPL = 0;
ECanaMboxes.MBOX2.MSGCTRL.bit.TPL = 0;
ECanaMboxes.MBOX24.MSGCTRL.bit.TPL = 0;
ECanaMboxes.MBOX29.MSGCTRL.bit.TPL = 0;
ECanaMboxes.MBOX12.MSGCTRL.bit.TPL = 0;
ECanaMboxes.MBOX16.MSGCTRL.bit.TPL = 0;
ECanaMboxes.MBOX31.MSGCTRL.bit.TPL = 0;
ECanaMboxes.MBOX22.MSGCTRL.bit.TPL = 0;
ECanaMboxes.MBOX19.MSGCTRL.bit.TPL = 0;
ECanaMboxes.MBOX21.MSGCTRL.bit.TPL = 0;
ECanaMboxes.MBOX1.MSGCTRL.bit.TPL = 0;
ECanaMboxes.MBOX30.MSGCTRL.bit.TPL = 0;
ECanaMboxes.MBOX28.MSGCTRL.bit.TPL = 0;
ECanaMboxes.MBOX25.MSGCTRL.bit.TPL = 0;
ECanaMboxes.MBOX10.MSGCTRL.bit.TPL = 0;
ECanaMboxes.MBOX3.MSGCTRL.bit.TPL = 0;
ECanaMboxes.MBOX8.MSGCTRL.bit.TPL = 0;
ECanaMboxes.MBOX5.MSGCTRL.bit.TPL = 0;
ECanaMboxes.MBOX14.MSGCTRL.bit.TPL = 0;
ECanaMboxes.MBOX6.MSGCTRL.bit.TPL = 0; */
/* Write to the mailbox RAM field of MBOX0 - 31 */
ECanaMboxes.MBOX0.MDL.all = 0x00000000;
ECanaMboxes.MBOX0.MDH.all = 0x00000000;
ECanaMboxes.MBOX1.MDL.all = 0x00000001;
ECanaMboxes.MBOX1.MDH.all = 0x00000000;
ECanaMboxes.MBOX2.MDL.all = 0x00000002;
ECanaMboxes.MBOX2.MDH.all = 0x00000000;
ECanaMboxes.MBOX3.MDL.all = 0x00000003;
ECanaMboxes.MBOX3.MDH.all = 0x00000000;
ECanaMboxes.MBOX4.MDL.all = 0x00000004;
ECanaMboxes.MBOX4.MDH.all = 0x00000000;
ECanaMboxes.MBOX5.MDL.all = 0x00000005;
ECanaMboxes.MBOX5.MDH.all = 0x00000000;
ECanaMboxes.MBOX6.MDL.all = 0x00000006;
ECanaMboxes.MBOX6.MDH.all = 0x00000000;
ECanaMboxes.MBOX7.MDL.all = 0x00000007;
ECanaMboxes.MBOX7.MDH.all = 0x00000000;
ECanaMboxes.MBOX8.MDL.all = 0x00000008;
ECanaMboxes.MBOX8.MDH.all = 0x00000000;
ECanaMboxes.MBOX9.MDL.all = 0x00000009;
ECanaMboxes.MBOX9.MDH.all = 0x00000000;
ECanaMboxes.MBOX10.MDL.all = 0x00000010;
ECanaMboxes.MBOX10.MDH.all = 0x00000000;
ECanaMboxes.MBOX11.MDL.all = 0x00000011;
ECanaMboxes.MBOX11.MDH.all = 0x00000000;
ECanaMboxes.MBOX12.MDL.all = 0x00000012;
ECanaMboxes.MBOX12.MDH.all = 0x00000000;
ECanaMboxes.MBOX13.MDL.all = 0x00000013;
ECanaMboxes.MBOX13.MDH.all = 0x00000000;
ECanaMboxes.MBOX14.MDL.all = 0x00000014;
ECanaMboxes.MBOX14.MDH.all = 0x00000000;
ECanaMboxes.MBOX15.MDL.all = 0x00000015;
ECanaMboxes.MBOX15.MDH.all = 0x00000000;
ECanaMboxes.MBOX16.MDL.all = 0x00000016;
ECanaMboxes.MBOX16.MDH.all = 0x00000000;
ECanaMboxes.MBOX17.MDL.all = 0x00000017;
ECanaMboxes.MBOX17.MDH.all = 0x00000000;
ECanaMboxes.MBOX18.MDL.all = 0x00000018;
ECanaMboxes.MBOX18.MDH.all = 0x00000000;
ECanaMboxes.MBOX19.MDL.all = 0x00000019;
ECanaMboxes.MBOX19.MDH.all = 0x00000000;
ECanaMboxes.MBOX20.MDL.all = 0x00000020;
ECanaMboxes.MBOX20.MDH.all = 0x00000000;
ECanaMboxes.MBOX21.MDL.all = 0x00000021;
ECanaMboxes.MBOX21.MDH.all = 0x00000000;
ECanaMboxes.MBOX22.MDL.all = 0x00000022;
ECanaMboxes.MBOX22.MDH.all = 0x00000000;
ECanaMboxes.MBOX23.MDL.all = 0x00000023;
ECanaMboxes.MBOX23.MDH.all = 0x00000000;
ECanaMboxes.MBOX24.MDL.all = 0x00000024;
ECanaMboxes.MBOX24.MDH.all = 0x00000000;
ECanaMboxes.MBOX25.MDL.all = 0x00000025;
ECanaMboxes.MBOX25.MDH.all = 0x00000000;
ECanaMboxes.MBOX26.MDL.all = 0x00000026;
ECanaMboxes.MBOX26.MDH.all = 0x00000000;
ECanaMboxes.MBOX27.MDL.all = 0x00000027;
ECanaMboxes.MBOX27.MDH.all = 0x00000000;
ECanaMboxes.MBOX28.MDL.all = 0x00000028;
ECanaMboxes.MBOX28.MDH.all = 0x00000000;
ECanaMboxes.MBOX29.MDL.all = 0x00000029;
ECanaMboxes.MBOX29.MDH.all = 0x00000000;
ECanaMboxes.MBOX30.MDL.all = 0x00000030;
ECanaMboxes.MBOX30.MDH.all = 0x00000000;
ECanaMboxes.MBOX31.MDL.all = 0x00000031;
ECanaMboxes.MBOX31.MDH.all = 0x00000000;
ECanaRegs.CANMIM.all = 0xFFFFFFFF;
/* Configure bit timing parameters */
ECanaRegs.CANMC.bit.CCR = 1 ; // Set CCR = 1
while(ECanaRegs.CANES.bit.CCE != 1 ) {} // Wait for CCE bit to be set..
ECanaRegs.CANBTC.bit.BRPREG = 9;
ECanaRegs.CANBTC.bit.TSEG2REG = 5;
ECanaRegs.CANBTC.bit.TSEG1REG = 7;
ECanaRegs.CANMC.bit.CCR = 0 ; // Set CCR = 0
while(ECanaRegs.CANES.bit.CCE != 0 ) {} // Wait for CCE bit to be cleared..
/* Begin transmitting */
ECanaRegs.CANTRS.all = 0xFFFFFFFF; // Set TRS for all transmit mailboxes
while(ECanaRegs.CANTA.all != 0xFFFFFFFF ) {} // Wait for all TAn bits to be set..
ECanaRegs.CANTA.all = 0xFFFFFFFF; // Clear all TAn
asm(" ESTOP0"); // Stop here after transmission
}
/*
Note 1: If all 32-bits are written to in a register, the register
may be written to without using a shadow register, as illustrated
in this code example.
CANalyzer configuration file: 1M80SPRX.cfg
... */
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