txloop_1.c

dsp2812中关于can总线的例程

/*********************************************************************
* Filename: TXLOOP.c                                                 *
*                                                                    *
* Description: TXLOOP - Transmit loop using any mailbox 	
* 
* Mailbox 5 is shown as an example...
* This program TRANSMITS data to another CAN module using MAILBOX5
* This program could either loop forever or transmit "n" # of times,	
* where "n" is the TXCOUNT value.
*          
* Last update: 12/23/2002
*********************************************************************/
#include "DSP281x_Device.h"     // DSP281x Headerfile Include File
#include "DSP281x_Examples.h"   // DSP281x Examples Include File
#define TXCOUNT  100  // Transmission will take place (TXCOUNT) times..

Uint32  i;
Uint32 loopcount=0;


main()
{

 /* Create a shadow register structure for the CAN control registers. This is
    needed, since, only 32-bit access is allowed to these registers. 16-bit access
    to these registers could potentially corrupt the register contents. This is
    especially true while writing to a bit (or group of bits) among bits 16 - 31 */
    struct ECAN_REGS ECanaShadow;

 // Step 1. Initialize System Control:
 // PLL, WatchDog, enable Peripheral Clocks 
 // This example function is found in the DSP281x_SysCtrl.c file.
    InitSysCtrl();

 // Step 2. Initalize GPIO: 
 // This example function is found in the DSP281x_Gpio.c file and
 // illustrates how to set the GPIO to it's default state.
 // InitGpio();  // Skipped for this example  

 // For this example, configure CAN pins using GPIO regs here
    EALLOW;
    GpioMuxRegs.GPFMUX.bit.CANTXA_GPIOF6 = 1;
    GpioMuxRegs.GPFMUX.bit.CANRXA_GPIOF7 = 1;
    EDIS;

 // Step 3. Clear all interrupts and initialize PIE vector table:
 // Disable CPU interrupts 
    DINT;

 // Initialize PIE control registers to their default state.
 // The default state is all PIE interrupts disabled and flags
 // are cleared.  
 // This function is found in the DSP281x_PieCtrl.c file.
    InitPieCtrl();

 // Disable CPU interrupts and clear all CPU interrupt flags:
    IER = 0x0000;
    IFR = 0x0000;

 // Initialize the PIE vector table with pointers to the shell Interrupt 
 // Service Routines (ISR).  
 // This will populate the entire table, even if the interrupt
 // is not used in this example.  This is useful for debug purposes.
 // The shell ISR routines are found in DSP281x_DefaultIsr.c.
 // This function is found in DSP281x_PieVect.c.
    InitPieVectTable();

 // Step 4. Initialize all the Device Peripherals:
 // This function is found in DSP281x_InitPeripherals.c
 // InitPeripherals(); // Not required for this example
 
 // Step 5. User specific code, enable interrupts:

 // eCAN control registers require 32-bit access. 
 // If you want to write to a single bit, the compiler may break this
 // access into a 16-bit access.  One solution, that is presented here,
 // is to use a shadow register to force the 32-bit access. 
     
 // Read the entire register into a shadow register.  This access
 // will be 32-bits.  Change the desired bit and copy the value back
 // to the eCAN register with a 32-bit write. 
   
 // Configure the eCAN RX and TX pins for eCAN transmissions
    EALLOW;
    ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all;
    ECanaShadow.CANTIOC.bit.TXFUNC = 1;
    ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all;

    ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all;
    ECanaShadow.CANRIOC.bit.RXFUNC = 1;
    ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all;
    EDIS;
     
/* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */
// HECC mode also enables time-stamping feature 
    ECanaRegs.CANMC.bit.SCB = 1;
/* Initialize all bits of 'Master Control Field' to zero */
// Some bits of MSGCTRL register come up in an unknown state. For proper operation,
// all bits (including reserved bits) of MSGCTRL must be initialized to zero
 
    ECanaMboxes.MBOX0.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX1.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX2.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX3.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX4.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX5.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX6.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX7.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX8.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX9.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX10.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX11.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX12.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX13.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX14.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX15.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX16.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX17.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX18.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX19.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX20.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX21.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX22.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX23.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX24.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX25.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX26.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX27.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX28.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX29.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX30.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX31.MSGCTRL.all = 0x00000000;    
    
 // TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
//	as a matter of precaution. 

/* Clear all TAn bits */      
	
	ECanaRegs.CANTA.all	= 0xFFFFFFFF;

/* Clear all RMPn bits */      
	
	ECanaRegs.CANRMP.all = 0xFFFFFFFF;
	
/* Clear all interrupt flag bits */      
	
	ECanaRegs.CANGIF0.all = 0xFFFFFFFF;
	ECanaRegs.CANGIF1.all = 0xFFFFFFFF;

/* Configure bit timing parameters */

	ECanaRegs.CANMC.bit.CCR = 1 ;            // Set CCR = 1
    
    while(ECanaRegs.CANES.bit.CCE != 1 ) {}   // Wait for CCE bit to be set..
    
    ECanaRegs.CANBTC.bit.BRPREG = 19;
    ECanaRegs.CANBTC.bit.TSEG2REG = 2;
    ECanaRegs.CANBTC.bit.TSEG1REG = 10;  
    
    ECanaRegs.CANMC.bit.CCR = 0 ;             // Set CCR = 0
    while(ECanaRegs.CANES.bit.CCE == !0 ) {}   // Wait for CCE bit to be cleared..

/* Disable all Mailboxes  */
	
 	ECanaRegs.CANME.all = 0;		// Required before writing the MSGIDs




/* Write to the MSGID field  */
    
    ECanaMboxes.MBOX5.MSGID.all = 0x2E15DC35; // Extended Identifier
       
/* Configure Mailbox under test as a Transmit mailbox */

	ECanaShadow.CANMD.all = ECanaRegs.CANMD.all;	
	ECanaShadow.CANMD.bit.MD5 = 0;
	ECanaRegs.CANMD.all = ECanaShadow.CANMD.all; 
	
/* Enable Mailbox under test */
	
	ECanaShadow.CANME.all = ECanaRegs.CANME.all;	
	ECanaShadow.CANME.bit.ME5 = 1;
	ECanaRegs.CANME.all = ECanaShadow.CANME.all; 
	
/* Write to DLC field in Master Control reg */

	ECanaMboxes.MBOX5.MSGCTRL.bit.DLC = 8;
	
/* Write to the mailbox RAM field */
    
     ECanaMboxes.MBOX5.MDL.all = 0x01234567;
	 ECanaMboxes.MBOX5.MDH.all = 0x89ABCDEF;	 
	 
   



/* Begin transmitting */

     //while(1) 							// Uncomment this line for infinite transmissions
     for(i=0; i < TXCOUNT; i++)				// Uncomment this line for finite transmissions			  	
    {
     
     ECanaShadow.CANTRS.all = 0; 	
     ECanaShadow.CANTRS.bit.TRS5 = 1;     // Set TRS for mailbox under test       
     ECanaRegs.CANTRS.all = ECanaShadow.CANTRS.all; 
         
     while(ECanaRegs.CANTA.bit.TA5 == 0 ) {}  // Wait for TA5 bit to be set..
     
     ECanaShadow.CANTA.all = 0; 	
     ECanaShadow.CANTA.bit.TA5 = 1;     	 // Clear TA5       
     ECanaRegs.CANTA.all = ECanaShadow.CANTA.all;
     
     loopcount ++; 			    
    }   

}

/* CANalyzer configuration file: 1M80SPRX.cfg... */