dlcrx_1.c

dsp2812中关于can总线的例程

/*********************************************************************
* Filename: DLCRX.c                                                
*                                                                    
* Description: Checks the operation of DLC field for a Receive mailbox. 	
* 
* DLC for a receive mailbox is irrelevant. The DLC field of the received
* frame is copied in the DLC field of the receive mailbox.
* Various values of DLC field are tried for mailbox 23. When the transmitting
* node transmits various data frames with differing DLC values, the correct
* number of bytes can be seen copied in the mailbox RAM window.
*          
* Last update: 12/24/2002
*********************************************************************/

#include "DSP281x_Device.h"     // DSP281x Headerfile Include File
#include "DSP281x_Examples.h"   // DSP281x Examples Include File

#define DLC_val 1   // DLC value attempted to be written into MSGCTRL register
					// Values 0 thru 8 may be tried..
Uint32	i;

main() 
{

 /* Create a shadow register structure for the CAN control registers. This is
    needed, since, only 32-bit access is allowed to these registers. 16-bit access
    to these registers could potentially corrupt the register contents. This is
    especially true while writing to a bit (or group of bits) among bits 16 - 31 */

    struct ECAN_REGS ECanaShadow;

    // Step 1. Initialize System Control:
    // PLL, WatchDog, enable Peripheral Clocks
    // This example function is found in the DSP281x_SysCtrl.c file.
    InitSysCtrl();

    // Step 2. Initalize GPIO: 
    // This example function is found in the DSP281x_Gpio.c file and
    // illustrates how to set the GPIO to it's default state.
    // InitGpio();  // Skipped for this example  

    // For this example, configure CAN pins using GPIO regs here
    EALLOW;
    GpioMuxRegs.GPFMUX.bit.CANTXA_GPIOF6 = 1;
    GpioMuxRegs.GPFMUX.bit.CANRXA_GPIOF7 = 1;
    EDIS;

    // Step 3. Clear all interrupts and initialize PIE vector table:
    // Disable CPU interrupts 
    DINT;

    // Initialize PIE control registers to their default state.
    // The default state is all PIE interrupts disabled and flags
    // are cleared.  
    // This function is found in the DSP281x_PieCtrl.c file.
    InitPieCtrl();

    // Disable CPU interrupts and clear all CPU interrupt flags:
    IER = 0x0000;
    IFR = 0x0000;

    // Initialize the PIE vector table with pointers to the shell Interrupt 
    // Service Routines (ISR).  
    // This will populate the entire table, even if the interrupt
    // is not used in this example.  This is useful for debug purposes.
    // The shell ISR routines are found in DSP281x_DefaultIsr.c.
    // This function is found in DSP281x_PieVect.c.
    InitPieVectTable();
  
    // Step 4. Initialize all the Device Peripherals:
    // This function is found in DSP281x_InitPeripherals.c
    // InitPeripherals(); // Not required for this example
 
    // Step 5. User specific code, enable interrupts:

    // eCAN control registers require 32-bit access. 
    // If you want to write to a single bit, the compiler may break this
    // access into a 16-bit access.  One solution, that is presented here,
    // is to use a shadow register to force the 32-bit access. 
     
    // Read the entire register into a shadow register.  This access
    // will be 32-bits.  Change the desired bit and copy the value back
    // to the eCAN register with a 32-bit write. 
   
    // Configure the eCAN RX and TX pins for eCAN transmissions
    EALLOW;
    ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all;
    ECanaShadow.CANTIOC.bit.TXFUNC = 1;
    ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all;

    ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all;
    ECanaShadow.CANRIOC.bit.RXFUNC = 1;
    ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all;
    EDIS;
     
    // Disable all Mailboxes
    // Since this write is to the entire register (instead of a bit
    // field) a shadow register is not required.
	
/* Write to the MSGID field  */
    
    ECanaMboxes.MBOX23.MSGID.all = 0x008C0000; // Std Identifier (ID = 23)
            
/* Configure Mailbox under test as a Receive mailbox */

	ECanaShadow.CANMD.all = ECanaRegs.CANMD.all;	
	ECanaShadow.CANMD.bit.MD23 = 1;
	ECanaRegs.CANMD.all = ECanaShadow.CANMD.all; 
	
/* Enable Mailbox under test */
	
	ECanaShadow.CANME.all = ECanaRegs.CANME.all;	
	ECanaShadow.CANME.bit.ME23 = 1;	
	ECanaRegs.CANME.all = ECanaShadow.CANME.all; 
	
/* Write to Master Control reg */   // Writes to MCF of a Rcv MBX are irrelevant
	
	ECanaMboxes.MBOX23.MSGCTRL.bit.DLC = DLC_val; // Writes to the DLC field of a Rcv MBX
		 								   // are not carried out
/* Begin Receiving */

    while(1) 						    			  	
    {
     while(ECanaRegs.CANRMP.bit.RMP23 == 0 ) {}  // Wait for RMP23 bit to be set..
     
     ECanaShadow.CANRMP.all = 0; 			    // See Note 1
     ECanaShadow.CANRMP.bit.RMP23 = 1;	    // Clear RMP23     
     ECanaRegs.CANRMP.all = ECanaShadow.CANRMP.all;
     
     asm (" NOP");        
    }   
}


/* 

Note 1: Initialize the "shadow-RMP" register to zero before setting any bit(s)
in order to clear it (them) in the RMP register. Otherwise, some other RMPn bit(s)
that is (are) set could be inadvertently cleared.

Note 2: Data frames with DLC values ranging from 0 - 8 may be transmitted 
from CANalyzer. Each time, the correct number of bytes will be received
and the DLC field updated accordingly.

CANalyzer configuration file: DLCRX.cfg
*/