dborx_1.c

dsp2812中关于can总线的例程

/*********************************************************************
* Filename: DBORX.c                                                
*                                                                    
* Description: Illustrates the operation of DBO field for a Receive mailbox. 	
* Mailbox 11 is used in this example.
*
* Last update: 12/24/2002
*********************************************************************/
#include "DSP281x_Device.h"     // DSP281x Headerfile Include File
#include "DSP281x_Examples.h"   // DSP281x Examples Include File

Uint32	i;



main() 
{

/* Create a shadow register structure for the CAN control registers. This is
 needed, since, only 32-bit access is allowed to these registers. 16-bit access
 to these registers could potentially corrupt the register contents. This is
 especially true while writing to a bit (or group of bits) among bits 16 - 31 */

struct ECAN_REGS ECanaShadow;

    // Step 1. Initialize System Control:
    // PLL, WatchDog, enable Peripheral Clocks
    // This example function is found in the DSP281x_SysCtrl.c file.
    InitSysCtrl();

    // Step 2. Initalize GPIO: 
    // This example function is found in the DSP281x_Gpio.c file and
    // illustrates how to set the GPIO to it's default state.
    // InitGpio();  // Skipped for this example  

    // For this example, configure CAN pins using GPIO regs here
    EALLOW;
    GpioMuxRegs.GPFMUX.bit.CANTXA_GPIOF6 = 1;
    GpioMuxRegs.GPFMUX.bit.CANRXA_GPIOF7 = 1;
    EDIS;

    // Step 3. Clear all interrupts and initialize PIE vector table:
    // Disable CPU interrupts 
    DINT;

    // Initialize PIE control registers to their default state.
    // The default state is all PIE interrupts disabled and flags
    // are cleared.  
    // This function is found in the DSP281x_PieCtrl.c file.
    InitPieCtrl();

    // Disable CPU interrupts and clear all CPU interrupt flags:
    IER = 0x0000;
    IFR = 0x0000;

    // Initialize the PIE vector table with pointers to the shell Interrupt 
    // Service Routines (ISR).  
    // This will populate the entire table, even if the interrupt
    // is not used in this example.  This is useful for debug purposes.
    // The shell ISR routines are found in DSP281x_DefaultIsr.c.
    // This function is found in DSP281x_PieVect.c.
    InitPieVectTable();
  
    // Step 4. Initialize all the Device Peripherals:
    // This function is found in DSP281x_InitPeripherals.c
    // InitPeripherals(); // Not required for this example
 
    // Step 5. User specific code, enable interrupts:

    // eCAN control registers require 32-bit access. 
    // If you want to write to a single bit, the compiler may break this
    // access into a 16-bit access.  One solution, that is presented here,
    // is to use a shadow register to force the 32-bit access. 
     
    // Read the entire register into a shadow register.  This access
    // will be 32-bits.  Change the desired bit and copy the value back
    // to the eCAN register with a 32-bit write. 
   
    // Configure the eCAN RX and TX pins for eCAN transmissions
    EALLOW;
    ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all;
    ECanaShadow.CANTIOC.bit.TXFUNC = 1;
    ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all;

    ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all;
    ECanaShadow.CANRIOC.bit.RXFUNC = 1;
    ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all;
    EDIS;
     
    // Disable all Mailboxes
    // Since this write is to the entire register (instead of a bit
    // field) a shadow register is not required.
	
/* Write to the MSGID field  */
    
    ECanaMboxes.MBOX11.MSGID.all = 0x00440000; // Std Identifier (ID = 11)
        
/* Configure Mailbox under test as a Receive mailbox */

	ECanaShadow.CANMD.all = ECanaRegs.CANMD.all;	
	ECanaShadow.CANMD.bit.MD11 = 1;
	ECanaRegs.CANMD.all = ECanaShadow.CANMD.all; 
	
/* Enable Mailbox under test */
	
	ECanaShadow.CANME.all = ECanaRegs.CANME.all;	
	ECanaShadow.CANME.bit.ME11 = 1;	
	ECanaRegs.CANME.all = ECanaShadow.CANME.all; 
	
/*Configure bit timing parameters*/
   
	ECanaRegs.CANMC.bit.CCR = 1 ;            	// Set CCR = 1
    
    while(ECanaRegs.CANES.bit.CCE != 1 ) {}   	// Wait for CCE bit to be set..
    
    ECanaRegs.CANBTC.bit.BRPREG = 9;
    ECanaRegs.CANBTC.bit.TSEG2REG = 5;
    ECanaRegs.CANBTC.bit.TSEG1REG = 7; 
    
    ECanaRegs.CANMC.bit.CCR = 0 ;              	// Set CCR = 0
    while(ECanaRegs.CANES.bit.CCE != 0 ) {}   	// Wait for CCE bit to be cleared..
    
/* Configure DBO bit */

	ECanaRegs.CANMC.bit.DBO = 1;
	
/* Begin Receiving */

    while(1) 						    			  	
    {
     while(ECanaRegs.CANRMP.bit.RMP11 == 0 ) {}  // Wait for RMP11 bit to be set..
     
     ECanaShadow.CANRMP.all = 0; 			    // See Note 1
     ECanaShadow.CANRMP.bit.RMP11 = 1;	    // Clear RMP11     
     ECanaRegs.CANRMP.all = ECanaShadow.CANRMP.all;
    }   
    
}


/* 

Note 1: Initialize the "shadow-RMP" register to zero before setting any bit(s)
in order to clear it (them) in the RMP register. Otherwise, some other RMPn bit(s)
that is (are) set could be inadvertently cleared.

Note 2: Following is the effect of DBO bit

Let CANalyzer transmit the following bytes in the sequence indicated:
01 02 03 04 05 06 07 08

When DBO = 1, the mailbox RAM contents be as follows...
615C: 0201
615D: 0403
615E: 0605
615F: 0807

When DBO = 0, the mailbox RAM contents be as follows...
615C: 0304
615D: 0102
615E: 0708
615F: 0506 
 
Use DBORX.cfg from CANalyzer.

*/