dbotx_1.c

dsp2812中关于can总线的例程

/*********************************************************************
* Filename: DBOTX.c                                                
*                                                                    
* Description: Illustrates the operation of DBO field for a Transmit mailbox. 	
* Mailbox 11 is used in this example 
*
* Last update: 12/24/2002
*********************************************************************/

#include "DSP281x_Device.h"     // DSP281x Headerfile Include File
#include "DSP281x_Examples.h"   // DSP281x Examples Include File

void error(int);

Uint32	i;



main() 
{

  /* Create a shadow register structure for the CAN control registers. This is
  needed, since, only 32-bit access is allowed to these registers. 16-bit access
  to these registers could potentially corrupt the register contents. This is
  especially true while writing to a bit (or group of bits) among bits 16 - 31 */

    struct ECAN_REGS ECanaShadow;
    // Step 1. Initialize System Control:
    // PLL, WatchDog, enable Peripheral Clocks
    // This example function is found in the DSP281x_SysCtrl.c file.
    InitSysCtrl();

    // Step 2. Initalize GPIO: 
    // This example function is found in the DSP281x_Gpio.c file and
    // illustrates how to set the GPIO to it's default state.
    // InitGpio();  // Skipped for this example  

    // For this example, configure CAN pins using GPIO regs here
    EALLOW;
    GpioMuxRegs.GPFMUX.bit.CANTXA_GPIOF6 = 1;
    GpioMuxRegs.GPFMUX.bit.CANRXA_GPIOF7 = 1;
    EDIS;

    // Step 3. Clear all interrupts and initialize PIE vector table:
    // Disable CPU interrupts 
    DINT;

    // Initialize PIE control registers to their default state.
    // The default state is all PIE interrupts disabled and flags
    // are cleared.  
    // This function is found in the DSP281x_PieCtrl.c file.
    InitPieCtrl();

    // Disable CPU interrupts and clear all CPU interrupt flags:
    IER = 0x0000;
    IFR = 0x0000;

    // Initialize the PIE vector table with pointers to the shell Interrupt 
    // Service Routines (ISR).  
    // This will populate the entire table, even if the interrupt
    // is not used in this example.  This is useful for debug purposes.
    // The shell ISR routines are found in DSP281x_DefaultIsr.c.
    // This function is found in DSP281x_PieVect.c.
    InitPieVectTable();
  
    // Step 4. Initialize all the Device Peripherals:
    // This function is found in DSP281x_InitPeripherals.c
    // InitPeripherals(); // Not required for this example
 
    // Step 5. User specific code, enable interrupts:

    // eCAN control registers require 32-bit access. 
    // If you want to write to a single bit, the compiler may break this
    // access into a 16-bit access.  One solution, that is presented here,
    // is to use a shadow register to force the 32-bit access. 
     
    // Read the entire register into a shadow register.  This access
    // will be 32-bits.  Change the desired bit and copy the value back
    // to the eCAN register with a 32-bit write. 
   
    // Configure the eCAN RX and TX pins for eCAN transmissions
    EALLOW;
    ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all;
    ECanaShadow.CANTIOC.bit.TXFUNC = 1;
    ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all;

    ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all;
    ECanaShadow.CANRIOC.bit.RXFUNC = 1;
    ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all;
    EDIS;
     
    // Disable all Mailboxes
    // Since this write is to the entire register (instead of a bit
    // field) a shadow register is not required.

/* Write to the MSGID field  */
    
    ECanaMboxes.MBOX11.MSGID.all = 0x80000011; // Ext Identifier (ID = 11)
    
/* Configure Mailbox under test as a Transmit mailbox */

	ECanaShadow.CANMD.all = ECanaRegs.CANMD.all;	
	ECanaShadow.CANMD.bit.MD11 = 0;
	ECanaRegs.CANMD.all = ECanaShadow.CANMD.all; 
	
/* Enable Mailbox under test */
	
	ECanaShadow.CANME.all = ECanaRegs.CANME.all;	
	ECanaShadow.CANME.bit.ME11 = 1;	
	ECanaRegs.CANME.all = ECanaShadow.CANME.all; 
	
/* Write to Master Control reg */
	
	ECanaMboxes.MBOX11.MSGCTRL.bit.DLC = 8;	
	
/* Write to the mailbox RAM field using 16-bit writes */
    
     
     ECanaMboxes.MBOX11.MDL.all = 0x04030201;
	
	 ECanaMboxes.MBOX11.MDH.all = 0x08070605;
	 	 	 
/* Configure DBO bit */

	ECanaRegs.CANMC.bit.DBO = 1;			// See Note 2
	
/* Begin transmitting */   
     
     ECanaShadow.CANTRS.all = 0;			// Set TRS bit 
     ECanaShadow.CANTRS.bit.TRS11 = 1;    
     ECanaRegs.CANTRS.all = ECanaShadow.CANTRS.all;
                  
     while(ECanaRegs.CANTA.bit.TA11 == 0 ) {}  // Wait for TA11 bit to be set..
     
     ECanaShadow.CANTA.all = 0; 			  // See Note 1
     ECanaShadow.CANTA.bit.TA11 = 1;		  // Clear TA11     
     ECanaRegs.CANTA.all = ECanaShadow.CANTA.all;
     
     asm("     ESTOP0");             
}


/* 

Note 1: Initialize the "shadow-TA register" to zero before setting any bit(s)
in order to clear it (them) in the TA register. Otherwise, some other TAn bit(s)
that is (are) set could be inadvertently cleared.

Note 2: Following is the effect of DBO bit

Let the mailbox RAM contents be as follows...
615C: 0201
615D: 0403
615E: 0605
615F: 0807

When DBO = 1, the bytes will be transmitted in the following sequence:
01 02 03 04 05 06 07 08

When DBO = 0, the bytes will be transmitted in the following sequence:
04 03 02 01 08 07 06 05

CANalyzer configuration file: 1M80spRx.cfg

*/