keyboardtest.tan.qmsg

键盘去抖动CPLD设计经过验证,可以直接用数码管显示,同时也希望大家给于新想法

{ "Info" "ITDB_FULL_TCO_RESULT" "CLK seven\[3\] debounce:keydeb\|jkt:jkf\|tq 44.000 ns register " "Info: tco from clock \"CLK\" to destination pin \"seven\[3\]\" through register \"debounce:keydeb\|jkt:jkf\|tq\" is 44.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 12.000 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 12.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns CLK 1 CLK PIN_83 12 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 12; CLK Node = 'CLK'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "src/keyboardtest.v" "" { Text "F:/ReceiverTest/keyboardtest/src/keyboardtest.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns cnt5:clkdiv\|lpm_counter:out1_rtl_1\|dffs\[4\] 2 REG LC45 5 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC45; Fanout = 5; REG Node = 'cnt5:clkdiv\|lpm_counter:out1_rtl_1\|dffs\[4\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.000 ns" { CLK cnt5:clkdiv|lpm_counter:out1_rtl_1|dffs[4] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 12.000 ns debounce:keydeb\|jkt:jkf\|tq 3 REG LC92 7 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 12.000 ns; Loc. = LC92; Fanout = 7; REG Node = 'debounce:keydeb\|jkt:jkf\|tq'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.000 ns" { cnt5:clkdiv|lpm_counter:out1_rtl_1|dffs[4] debounce:keydeb|jkt:jkf|tq } "NODE_NAME" } } { "src/jkt.v" "" { Text "F:/ReceiverTest/keyboardtest/src/jkt.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns ( 83.33 % ) " "Info: Total cell delay = 10.000 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 16.67 % ) " "Info: Total interconnect delay = 2.000 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.000 ns" { CLK cnt5:clkdiv|lpm_counter:out1_rtl_1|dffs[4] debounce:keydeb|jkt:jkf|tq } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "12.000 ns" { CLK CLK~out cnt5:clkdiv|lpm_counter:out1_rtl_1|dffs[4] debounce:keydeb|jkt:jkf|tq } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "src/jkt.v" "" { Text "F:/ReceiverTest/keyboardtest/src/jkt.v" 25 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "31.000 ns + Longest register pin " "Info: + Longest register to pin delay is 31.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns debounce:keydeb\|jkt:jkf\|tq 1 REG LC92 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC92; Fanout = 7; REG Node = 'debounce:keydeb\|jkt:jkf\|tq'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { debounce:keydeb|jkt:jkf|tq } "NODE_NAME" } } { "src/jkt.v" "" { Text "F:/ReceiverTest/keyboardtest/src/jkt.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 9.000 ns keypress_det:key_select\|always0~55 2 COMB LC81 13 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 9.000 ns; Loc. = LC81; Fanout = 13; COMB Node = 'keypress_det:key_select\|always0~55'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.000 ns" { debounce:keydeb|jkt:jkf|tq keypress_det:key_select|always0~55 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(9.000 ns) 18.000 ns keypress_det:key_select\|REAL_code\[3\]~68 3 COMB LOOP LC33 24 " "Info: 3: + IC(0.000 ns) + CELL(9.000 ns) = 18.000 ns; Loc. = LC33; Fanout = 24; COMB LOOP Node = 'keypress_det:key_select\|REAL_code\[3\]~68'" { { "Info" "ITDB_PART_OF_SCC" "keypress_det:key_select\|REAL_code\[3\]~68 LC33 " "Info: Loc. = LC33; Node \"keypress_det:key_select\|REAL_code\[3\]~68\"" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { keypress_det:key_select|REAL_code[3]~68 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { keypress_det:key_select|REAL_code[3]~68 } "NODE_NAME" } } { "src/keypress_det.v" "" { Text "F:/ReceiverTest/keyboardtest/src/keypress_det.v" 41 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.000 ns" { keypress_det:key_select|always0~55 keypress_det:key_select|REAL_code[3]~68 } "NODE_NAME" } } { "src/keypress_det.v" "" { Text "F:/ReceiverTest/keyboardtest/src/keypress_det.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 27.000 ns sevenseg:SEVEN_DSP\|WideOr3~157 4 COMB LC91 1 " "Info: 4: + IC(2.000 ns) + CELL(7.000 ns) = 27.000 ns; Loc. = LC91; Fanout = 1; COMB Node = 'sevenseg:SEVEN_DSP\|WideOr3~157'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.000 ns" { keypress_det:key_select|REAL_code[3]~68 sevenseg:SEVEN_DSP|WideOr3~157 } "NODE_NAME" } } { "src/sevenseg.v" "" { Text "F:/ReceiverTest/keyboardtest/src/sevenseg.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 31.000 ns seven\[3\] 5 PIN PIN_58 0 " "Info: 5: + IC(0.000 ns) + CELL(4.000 ns) = 31.000 ns; Loc. = PIN_58; Fanout = 0; PIN Node = 'seven\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.000 ns" { sevenseg:SEVEN_DSP|WideOr3~157 seven[3] } "NODE_NAME" } } { "src/keyboardtest.v" "" { Text "F:/ReceiverTest/keyboardtest/src/keyboardtest.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "27.000 ns ( 87.10 % ) " "Info: Total cell delay = 27.000 ns ( 87.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns ( 12.90 % ) " "Info: Total interconnect delay = 4.000 ns ( 12.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "31.000 ns" { debounce:keydeb|jkt:jkf|tq keypress_det:key_select|always0~55 keypress_det:key_select|REAL_code[3]~68 sevenseg:SEVEN_DSP|WideOr3~157 seven[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "31.000 ns" { debounce:keydeb|jkt:jkf|tq keypress_det:key_select|always0~55 keypress_det:key_select|REAL_code[3]~68 sevenseg:SEVEN_DSP|WideOr3~157 seven[3] } { 0.000ns 2.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 7.000ns 9.000ns 7.000ns 4.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.000 ns" { CLK cnt5:clkdiv|lpm_counter:out1_rtl_1|dffs[4] debounce:keydeb|jkt:jkf|tq } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "12.000 ns" { CLK CLK~out cnt5:clkdiv|lpm_counter:out1_rtl_1|dffs[4] debounce:keydeb|jkt:jkf|tq } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "31.000 ns" { debounce:keydeb|jkt:jkf|tq keypress_det:key_select|always0~55 keypress_det:key_select|REAL_code[3]~68 sevenseg:SEVEN_DSP|WideOr3~157 seven[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "31.000 ns" { debounce:keydeb|jkt:jkf|tq keypress_det:key_select|always0~55 keypress_det:key_select|REAL_code[3]~68 sevenseg:SEVEN_DSP|WideOr3~157 seven[3] } { 0.000ns 2.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 7.000ns 9.000ns 7.000ns 4.000ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "ROW_in\[1\] seven\[3\] 33.000 ns Longest " "Info: Longest tpd from source pin \"ROW_in\[1\]\" to destination pin \"seven\[3\]\" is 33.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns ROW_in\[1\] 1 PIN PIN_36 5 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_36; Fanout = 5; PIN Node = 'ROW_in\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ROW_in[1] } "NODE_NAME" } } { "src/keyboardtest.v" "" { Text "F:/ReceiverTest/keyboardtest/src/keyboardtest.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 11.000 ns keypress_det:key_select\|always0~55 2 COMB LC81 13 " "Info: 2: + IC(2.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC81; Fanout = 13; COMB Node = 'keypress_det:key_select\|always0~55'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.000 ns" { ROW_in[1] keypress_det:key_select|always0~55 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(9.000 ns) 20.000 ns keypress_det:key_select\|REAL_code\[3\]~68 3 COMB LOOP LC33 24 " "Info: 3: + IC(0.000 ns) + CELL(9.000 ns) = 20.000 ns; Loc. = LC33; Fanout = 24; COMB LOOP Node = 'keypress_det:key_select\|REAL_code\[3\]~68'" { { "Info" "ITDB_PART_OF_SCC" "keypress_det:key_select\|REAL_code\[3\]~68 LC33 " "Info: Loc. = LC33; Node \"keypress_det:key_select\|REAL_code\[3\]~68\"" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { keypress_det:key_select|REAL_code[3]~68 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { keypress_det:key_select|REAL_code[3]~68 } "NODE_NAME" } } { "src/keypress_det.v" "" { Text "F:/ReceiverTest/keyboardtest/src/keypress_det.v" 41 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.000 ns" { keypress_det:key_select|always0~55 keypress_det:key_select|REAL_code[3]~68 } "NODE_NAME" } } { "src/keypress_det.v" "" { Text "F:/ReceiverTest/keyboardtest/src/keypress_det.v" 41 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 29.000 ns sevenseg:SEVEN_DSP\|WideOr3~157 4 COMB LC91 1 " "Info: 4: + IC(2.000 ns) + CELL(7.000 ns) = 29.000 ns; Loc. = LC91; Fanout = 1; COMB Node = 'sevenseg:SEVEN_DSP\|WideOr3~157'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.000 ns" { keypress_det:key_select|REAL_code[3]~68 sevenseg:SEVEN_DSP|WideOr3~157 } "NODE_NAME" } } { "src/sevenseg.v" "" { Text "F:/ReceiverTest/keyboardtest/src/sevenseg.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 33.000 ns seven\[3\] 5 PIN PIN_58 0 " "Info: 5: + IC(0.000 ns) + CELL(4.000 ns) = 33.000 ns; Loc. = PIN_58; Fanout = 0; PIN Node = 'seven\[3\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.000 ns" { sevenseg:SEVEN_DSP|WideOr3~157 seven[3] } "NODE_NAME" } } { "src/keyboardtest.v" "" { Text "F:/ReceiverTest/keyboardtest/src/keyboardtest.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "29.000 ns ( 87.88 % ) " "Info: Total cell delay = 29.000 ns ( 87.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns ( 12.12 % ) " "Info: Total interconnect delay = 4.000 ns ( 12.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "33.000 ns" { ROW_in[1] keypress_det:key_select|always0~55 keypress_det:key_select|REAL_code[3]~68 sevenseg:SEVEN_DSP|WideOr3~157 seven[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "33.000 ns" { ROW_in[1] ROW_in[1]~out keypress_det:key_select|always0~55 keypress_det:key_select|REAL_code[3]~68 sevenseg:SEVEN_DSP|WideOr3~157 seven[3] } { 0.000ns 0.000ns 2.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 2.000ns 7.000ns 9.000ns 7.000ns 4.000ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "debounce:keydeb\|DEL1 ROW_in\[2\] CLK 6.000 ns register " "Info: th for register \"debounce:keydeb\|DEL1\" (data pin = \"ROW_in\[2\]\", clock pin = \"CLK\") is 6.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 12.000 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 12.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns CLK 1 CLK PIN_83 12 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 12; CLK Node = 'CLK'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "src/keyboardtest.v" "" { Text "F:/ReceiverTest/keyboardtest/src/keyboardtest.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns cnt5:clkdiv\|lpm_counter:out1_rtl_1\|dffs\[4\] 2 REG LC45 5 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC45; Fanout = 5; REG Node = 'cnt5:clkdiv\|lpm_counter:out1_rtl_1\|dffs\[4\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.000 ns" { CLK cnt5:clkdiv|lpm_counter:out1_rtl_1|dffs[4] } "NODE_NAME" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 268 9 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 12.000 ns debounce:keydeb\|DEL1 3 REG LC84 3 " "Info: 3: + IC(2.000 ns) + CELL(6.000 ns) = 12.000 ns; Loc. = LC84; Fanout = 3; REG Node = 'debounce:keydeb\|DEL1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.000 ns" { cnt5:clkdiv|lpm_counter:out1_rtl_1|dffs[4] debounce:keydeb|DEL1 } "NODE_NAME" } } { "src/debounce.v" "" { Text "F:/ReceiverTest/keyboardtest/src/debounce.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns ( 83.33 % ) " "Info: Total cell delay = 10.000 ns ( 83.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 16.67 % ) " "Info: Total interconnect delay = 2.000 ns ( 16.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.000 ns" { CLK cnt5:clkdiv|lpm_counter:out1_rtl_1|dffs[4] debounce:keydeb|DEL1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "12.000 ns" { CLK CLK~out cnt5:clkdiv|lpm_counter:out1_rtl_1|dffs[4] debounce:keydeb|DEL1 } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "4.000 ns + " "Info: + Micro hold delay of destination is 4.000 ns" {  } { { "src/debounce.v" "" { Text "F:/ReceiverTest/keyboardtest/src/debounce.v" 21 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns - Shortest pin register " "Info: - Shortest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns ROW_in\[2\] 1 PIN PIN_37 6 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_37; Fanout = 6; PIN Node = 'ROW_in\[2\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ROW_in[2] } "NODE_NAME" } } { "src/keyboardtest.v" "" { Text "F:/ReceiverTest/keyboardtest/src/keyboardtest.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns debounce:keydeb\|DEL1 2 REG LC84 3 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC84; Fanout = 3; REG Node = 'debounce:keydeb\|DEL1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.000 ns" { ROW_in[2] debounce:keydeb|DEL1 } "NODE_NAME" } } { "src/debounce.v" "" { Text "F:/ReceiverTest/keyboardtest/src/debounce.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns ( 80.00 % ) " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 20.00 % ) " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.000 ns" { ROW_in[2] debounce:keydeb|DEL1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "10.000 ns" { ROW_in[2] ROW_in[2]~out debounce:keydeb|DEL1 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "12.000 ns" { CLK cnt5:clkdiv|lpm_counter:out1_rtl_1|dffs[4] debounce:keydeb|DEL1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "12.000 ns" { CLK CLK~out cnt5:clkdiv|lpm_counter:out1_rtl_1|dffs[4] debounce:keydeb|DEL1 } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 6.000ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.000 ns" { ROW_in[2] debounce:keydeb|DEL1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "10.000 ns" { ROW_in[2] ROW_in[2]~out debounce:keydeb|DEL1 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Aug 23 12:13:22 2007 " "Info: Processing ended: Thu Aug 23 12:13:22 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}