setpmoto.tan.qmsg

这是一个用VHDL语言写的电动机程序,希望对大家有用

{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "GCLK3 8 " "Warning: Circuit may not operate. Detected 8 non-operational path(s) clocked by clock \"GCLK3\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "step_motor:inst1\|PHASE step_motor:inst1\|ind_coil\[3\] GCLK3 2.291 ns " "Info: Found hold time violation between source  pin or register \"step_motor:inst1\|PHASE\" and destination pin or register \"step_motor:inst1\|ind_coil\[3\]\" for clock \"GCLK3\" (Hold time is 2.291 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "4.584 ns + Largest " "Info: + Largest clock skew is 4.584 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "GCLK3 destination 12.548 ns + Longest register " "Info: + Longest clock path from clock \"GCLK3\" to destination register is 12.548 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns GCLK3 1 CLK PIN_64 18 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_64; Fanout = 18; CLK Node = 'GCLK3'" {  } { { "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" "" { Report "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" Compiler "SETPMOTO" "UNKNOWN" "V1" "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO.quartus_db" { Floorplan "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/" "" "" { GCLK3 } "NODE_NAME" } "" } } { "SETPMOTO.bdf" "" { Schematic "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/SETPMOTO.bdf" { { 144 -56 112 160 "GCLK3" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.377 ns) + CELL(1.294 ns) 3.834 ns fenping:inst\|QN\[16\] 2 REG LC_X3_Y3_N7 27 " "Info: 2: + IC(1.377 ns) + CELL(1.294 ns) = 3.834 ns; Loc. = LC_X3_Y3_N7; Fanout = 27; REG Node = 'fenping:inst\|QN\[16\]'" {  } { { "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" "" { Report "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" Compiler "SETPMOTO" "UNKNOWN" "V1" "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO.quartus_db" { Floorplan "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/" "" "2.671 ns" { GCLK3 fenping:inst|QN[16] } "NODE_NAME" } "" } } { "fenping.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/fenping.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.212 ns) + CELL(1.294 ns) 8.340 ns step_motor:inst1\|clk_scan 3 REG LC_X5_Y3_N9 9 " "Info: 3: + IC(3.212 ns) + CELL(1.294 ns) = 8.340 ns; Loc. = LC_X5_Y3_N9; Fanout = 9; REG Node = 'step_motor:inst1\|clk_scan'" {  } { { "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" "" { Report "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" Compiler "SETPMOTO" "UNKNOWN" "V1" "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO.quartus_db" { Floorplan "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/" "" "4.506 ns" { fenping:inst|QN[16] step_motor:inst1|clk_scan } "NODE_NAME" } "" } } { "step_motor.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/step_motor.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.290 ns) + CELL(0.918 ns) 12.548 ns step_motor:inst1\|ind_coil\[3\] 4 REG LC_X5_Y1_N7 4 " "Info: 4: + IC(3.290 ns) + CELL(0.918 ns) = 12.548 ns; Loc. = LC_X5_Y1_N7; Fanout = 4; REG Node = 'step_motor:inst1\|ind_coil\[3\]'" {  } { { "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" "" { Report "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" Compiler "SETPMOTO" "UNKNOWN" "V1" "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO.quartus_db" { Floorplan "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/" "" "4.208 ns" { step_motor:inst1|clk_scan step_motor:inst1|ind_coil[3] } "NODE_NAME" } "" } } { "step_motor.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/step_motor.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.669 ns 37.21 % " "Info: Total cell delay = 4.669 ns ( 37.21 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.879 ns 62.79 % " "Info: Total interconnect delay = 7.879 ns ( 62.79 % )" {  } {  } 0}  } { { "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" "" { Report "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" Compiler "SETPMOTO" "UNKNOWN" "V1" "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO.quartus_db" { Floorplan "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/" "" "12.548 ns" { GCLK3 fenping:inst|QN[16] step_motor:inst1|clk_scan step_motor:inst1|ind_coil[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "12.548 ns" { GCLK3 GCLK3~combout fenping:inst|QN[16] step_motor:inst1|clk_scan step_motor:inst1|ind_coil[3] } { 0.0ns 0.0ns 1.377ns 3.212ns 3.29ns } { 0.0ns 1.163ns 1.294ns 1.294ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "GCLK3 source 7.964 ns - Shortest register " "Info: - Shortest clock path from clock \"GCLK3\" to source register is 7.964 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns GCLK3 1 CLK PIN_64 18 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_64; Fanout = 18; CLK Node = 'GCLK3'" {  } { { "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" "" { Report "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" Compiler "SETPMOTO" "UNKNOWN" "V1" "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO.quartus_db" { Floorplan "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/" "" "" { GCLK3 } "NODE_NAME" } "" } } { "SETPMOTO.bdf" "" { Schematic "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/SETPMOTO.bdf" { { 144 -56 112 160 "GCLK3" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.377 ns) + CELL(1.294 ns) 3.834 ns fenping:inst\|QN\[16\] 2 REG LC_X3_Y3_N7 27 " "Info: 2: + IC(1.377 ns) + CELL(1.294 ns) = 3.834 ns; Loc. = LC_X3_Y3_N7; Fanout = 27; REG Node = 'fenping:inst\|QN\[16\]'" {  } { { "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" "" { Report "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" Compiler "SETPMOTO" "UNKNOWN" "V1" "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO.quartus_db" { Floorplan "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/" "" "2.671 ns" { GCLK3 fenping:inst|QN[16] } "NODE_NAME" } "" } } { "fenping.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/fenping.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.212 ns) + CELL(0.918 ns) 7.964 ns step_motor:inst1\|PHASE 3 REG LC_X5_Y1_N3 5 " "Info: 3: + IC(3.212 ns) + CELL(0.918 ns) = 7.964 ns; Loc. = LC_X5_Y1_N3; Fanout = 5; REG Node = 'step_motor:inst1\|PHASE'" {  } { { "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" "" { Report "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" Compiler "SETPMOTO" "UNKNOWN" "V1" "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO.quartus_db" { Floorplan "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/" "" "4.130 ns" { fenping:inst|QN[16] step_motor:inst1|PHASE } "NODE_NAME" } "" } } { "step_motor.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/step_motor.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns 42.38 % " "Info: Total cell delay = 3.375 ns ( 42.38 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.589 ns 57.62 % " "Info: Total interconnect delay = 4.589 ns ( 57.62 % )" {  } {  } 0}  } { { "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" "" { Report "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" Compiler "SETPMOTO" "UNKNOWN" "V1" "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO.quartus_db" { Floorplan "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/" "" "7.964 ns" { GCLK3 fenping:inst|QN[16] step_motor:inst1|PHASE } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.964 ns" { GCLK3 GCLK3~combout fenping:inst|QN[16] step_motor:inst1|PHASE } { 0.0ns 0.0ns 1.377ns 3.212ns } { 0.0ns 1.163ns 1.294ns 0.918ns } } }  } 0}  } { { "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" "" { Report "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" Compiler "SETPMOTO" "UNKNOWN" "V1" "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO.quartus_db" { Floorplan "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/" "" "12.548 ns" { GCLK3 fenping:inst|QN[16] step_motor:inst1|clk_scan step_motor:inst1|ind_coil[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "12.548 ns" { GCLK3 GCLK3~combout fenping:inst|QN[16] step_motor:inst1|clk_scan step_motor:inst1|ind_coil[3] } { 0.0ns 0.0ns 1.377ns 3.212ns 3.29ns } { 0.0ns 1.163ns 1.294ns 1.294ns 0.918ns } } } { "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" "" { Report "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" Compiler "SETPMOTO" "UNKNOWN" "V1" "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO.quartus_db" { Floorplan "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/" "" "7.964 ns" { GCLK3 fenping:inst|QN[16] step_motor:inst1|PHASE } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.964 ns" { GCLK3 GCLK3~combout fenping:inst|QN[16] step_motor:inst1|PHASE } { 0.0ns 0.0ns 1.377ns 3.212ns } { 0.0ns 1.163ns 1.294ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns - " "Info: - Micro clock to output delay of source is 0.376 ns" {  } { { "step_motor.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/step_motor.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.138 ns - Shortest register register " "Info: - Shortest register to register delay is 2.138 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns step_motor:inst1\|PHASE 1 REG LC_X5_Y1_N3 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y1_N3; Fanout = 5; REG Node = 'step_motor:inst1\|PHASE'" {  } { { "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" "" { Report "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" Compiler "SETPMOTO" "UNKNOWN" "V1" "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO.quartus_db" { Floorplan "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/" "" "" { step_motor:inst1|PHASE } "NODE_NAME" } "" } } { "step_motor.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/step_motor.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.895 ns) + CELL(1.243 ns) 2.138 ns step_motor:inst1\|ind_coil\[3\] 2 REG LC_X5_Y1_N7 4 " "Info: 2: + IC(0.895 ns) + CELL(1.243 ns) = 2.138 ns; Loc. = LC_X5_Y1_N7; Fanout = 4; REG Node = 'step_motor:inst1\|ind_coil\[3\]'" {  } { { "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" "" { Report "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" Compiler "SETPMOTO" "UNKNOWN" "V1" "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO.quartus_db" { Floorplan "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/" "" "2.138 ns" { step_motor:inst1|PHASE step_motor:inst1|ind_coil[3] } "NODE_NAME" } "" } } { "step_motor.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/step_motor.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.243 ns 58.14 % " "Info: Total cell delay = 1.243 ns ( 58.14 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.895 ns 41.86 % " "Info: Total interconnect delay = 0.895 ns ( 41.86 % )" {  } {  } 0}  } { { "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" "" { Report "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" Compiler "SETPMOTO" "UNKNOWN" "V1" "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO.quartus_db" { Floorplan "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/" "" "2.138 ns" { step_motor:inst1|PHASE step_motor:inst1|ind_coil[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.138 ns" { step_motor:inst1|PHASE step_motor:inst1|ind_coil[3] } { 0.0ns 0.895ns } { 0.0ns 1.243ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "step_motor.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/step_motor.vhd" 16 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "step_motor.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/step_motor.vhd" 18 -1 0 } } { "step_motor.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/step_motor.vhd" 16 -1 0 } }  } 0}  } { { "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" "" { Report "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" Compiler "SETPMOTO" "UNKNOWN" "V1" "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO.quartus_db" { Floorplan "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/" "" "12.548 ns" { GCLK3 fenping:inst|QN[16] step_motor:inst1|clk_scan step_motor:inst1|ind_coil[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "12.548 ns" { GCLK3 GCLK3~combout fenping:inst|QN[16] step_motor:inst1|clk_scan step_motor:inst1|ind_coil[3] } { 0.0ns 0.0ns 1.377ns 3.212ns 3.29ns } { 0.0ns 1.163ns 1.294ns 1.294ns 0.918ns } } } { "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" "" { Report "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" Compiler "SETPMOTO" "UNKNOWN" "V1" "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO.quartus_db" { Floorplan "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/" "" "7.964 ns" { GCLK3 fenping:inst|QN[16] step_motor:inst1|PHASE } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.964 ns" { GCLK3 GCLK3~combout fenping:inst|QN[16] step_motor:inst1|PHASE } { 0.0ns 0.0ns 1.377ns 3.212ns } { 0.0ns 1.163ns 1.294ns 0.918ns } } } { "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" "" { Report "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" Compiler "SETPMOTO" "UNKNOWN" "V1" "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO.quartus_db" { Floorplan "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/" "" "2.138 ns" { step_motor:inst1|PHASE step_motor:inst1|ind_coil[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.138 ns" { step_motor:inst1|PHASE step_motor:inst1|ind_coil[3] } { 0.0ns 0.895ns } { 0.0ns 1.243ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "step_motor:inst1\|PHASE P GCLK3 -0.362 ns register " "Info: tsu for register \"step_motor:inst1\|PHASE\" (data pin = \"P\", clock pin = \"GCLK3\") is -0.362 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.269 ns + Longest pin register " "Info: + Longest pin to register delay is 7.269 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns P 1 PIN PIN_48 2 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_48; Fanout = 2; PIN Node = 'P'" {  } { { "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" "" { Report "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" Compiler "SETPMOTO" "UNKNOWN" "V1" "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO.quartus_db" { Floorplan "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/" "" "" { P } "NODE_NAME" } "" } } { "SETPMOTO.bdf" "" { Schematic "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/SETPMOTO.bdf" { { 160 208 376 176 "P" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.031 ns) + CELL(0.200 ns) 5.363 ns step_motor:inst1\|B~1 2 COMB LC_X5_Y1_N6 1 " "Info: 2: + IC(4.031 ns) + CELL(0.200 ns) = 5.363 ns; Loc. = LC_X5_Y1_N6; Fanout = 1; COMB Node = 'step_motor:inst1\|B~1'" {  } { { "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" "" { Report "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" Compiler "SETPMOTO" "UNKNOWN" "V1" "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO.quartus_db" { Floorplan "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/" "" "4.231 ns" { P step_motor:inst1|B~1 } "NODE_NAME" } "" } } { "step_motor.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/step_motor.vhd" 65 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.663 ns) + CELL(1.243 ns) 7.269 ns step_motor:inst1\|PHASE 3 REG LC_X5_Y1_N3 5 " "Info: 3: + IC(0.663 ns) + CELL(1.243 ns) = 7.269 ns; Loc. = LC_X5_Y1_N3; Fanout = 5; REG Node = 'step_motor:inst1\|PHASE'" {  } { { "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" "" { Report "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" Compiler "SETPMOTO" "UNKNOWN" "V1" "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO.quartus_db" { Floorplan "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/" "" "1.906 ns" { step_motor:inst1|B~1 step_motor:inst1|PHASE } "NODE_NAME" } "" } } { "step_motor.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/step_motor.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.575 ns 35.42 % " "Info: Total cell delay = 2.575 ns ( 35.42 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.694 ns 64.58 % " "Info: Total interconnect delay = 4.694 ns ( 64.58 % )" {  } {  } 0}  } { { "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" "" { Report "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" Compiler "SETPMOTO" "UNKNOWN" "V1" "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO.quartus_db" { Floorplan "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/" "" "7.269 ns" { P step_motor:inst1|B~1 step_motor:inst1|PHASE } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.269 ns" { P P~combout step_motor:inst1|B~1 step_motor:inst1|PHASE } { 0.000ns 0.000ns 4.031ns 0.663ns } { 0.000ns 1.132ns 0.200ns 1.243ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "step_motor.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/step_motor.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "GCLK3 destination 7.964 ns - Shortest register " "Info: - Shortest clock path from clock \"GCLK3\" to destination register is 7.964 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns GCLK3 1 CLK PIN_64 18 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_64; Fanout = 18; CLK Node = 'GCLK3'" {  } { { "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" "" { Report "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" Compiler "SETPMOTO" "UNKNOWN" "V1" "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO.quartus_db" { Floorplan "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/" "" "" { GCLK3 } "NODE_NAME" } "" } } { "SETPMOTO.bdf" "" { Schematic "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/SETPMOTO.bdf" { { 144 -56 112 160 "GCLK3" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.377 ns) + CELL(1.294 ns) 3.834 ns fenping:inst\|QN\[16\] 2 REG LC_X3_Y3_N7 27 " "Info: 2: + IC(1.377 ns) + CELL(1.294 ns) = 3.834 ns; Loc. = LC_X3_Y3_N7; Fanout = 27; REG Node = 'fenping:inst\|QN\[16\]'" {  } { { "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" "" { Report "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" Compiler "SETPMOTO" "UNKNOWN" "V1" "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO.quartus_db" { Floorplan "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/" "" "2.671 ns" { GCLK3 fenping:inst|QN[16] } "NODE_NAME" } "" } } { "fenping.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/fenping.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.212 ns) + CELL(0.918 ns) 7.964 ns step_motor:inst1\|PHASE 3 REG LC_X5_Y1_N3 5 " "Info: 3: + IC(3.212 ns) + CELL(0.918 ns) = 7.964 ns; Loc. = LC_X5_Y1_N3; Fanout = 5; REG Node = 'step_motor:inst1\|PHASE'" {  } { { "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" "" { Report "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" Compiler "SETPMOTO" "UNKNOWN" "V1" "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO.quartus_db" { Floorplan "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/" "" "4.130 ns" { fenping:inst|QN[16] step_motor:inst1|PHASE } "NODE_NAME" } "" } } { "step_motor.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/step_motor.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns 42.38 % " "Info: Total cell delay = 3.375 ns ( 42.38 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.589 ns 57.62 % " "Info: Total interconnect delay = 4.589 ns ( 57.62 % )" {  } {  } 0}  } { { "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" "" { Report "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" Compiler "SETPMOTO" "UNKNOWN" "V1" "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO.quartus_db" { Floorplan "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/" "" "7.964 ns" { GCLK3 fenping:inst|QN[16] step_motor:inst1|PHASE } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.964 ns" { GCLK3 GCLK3~combout fenping:inst|QN[16] step_motor:inst1|PHASE } { 0.000ns 0.000ns 1.377ns 3.212ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0}  } { { "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" "" { Report "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" Compiler "SETPMOTO" "UNKNOWN" "V1" "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO.quartus_db" { Floorplan "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/" "" "7.269 ns" { P step_motor:inst1|B~1 step_motor:inst1|PHASE } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.269 ns" { P P~combout step_motor:inst1|B~1 step_motor:inst1|PHASE } { 0.000ns 0.000ns 4.031ns 0.663ns } { 0.000ns 1.132ns 0.200ns 1.243ns } } } { "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" "" { Report "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" Compiler "SETPMOTO" "UNKNOWN" "V1" "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO.quartus_db" { Floorplan "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/" "" "7.964 ns" { GCLK3 fenping:inst|QN[16] step_motor:inst1|PHASE } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.964 ns" { GCLK3 GCLK3~combout fenping:inst|QN[16] step_motor:inst1|PHASE } { 0.000ns 0.000ns 1.377ns 3.212ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "GCLK3 SD\[3\] step_motor:inst1\|t\[3\] 18.119 ns register " "Info: tco from clock \"GCLK3\" to destination pin \"SD\[3\]\" through register \"step_motor:inst1\|t\[3\]\" is 18.119 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "GCLK3 source 12.548 ns + Longest register " "Info: + Longest clock path from clock \"GCLK3\" to source register is 12.548 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns GCLK3 1 CLK PIN_64 18 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_64; Fanout = 18; CLK Node = 'GCLK3'" {  } { { "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" "" { Report "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" Compiler "SETPMOTO" "UNKNOWN" "V1" "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO.quartus_db" { Floorplan "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/" "" "" { GCLK3 } "NODE_NAME" } "" } } { "SETPMOTO.bdf" "" { Schematic "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/SETPMOTO.bdf" { { 144 -56 112 160 "GCLK3" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.377 ns) + CELL(1.294 ns) 3.834 ns fenping:inst\|QN\[16\] 2 REG LC_X3_Y3_N7 27 " "Info: 2: + IC(1.377 ns) + CELL(1.294 ns) = 3.834 ns; Loc. = LC_X3_Y3_N7; Fanout = 27; REG Node = 'fenping:inst\|QN\[16\]'" {  } { { "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" "" { Report "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" Compiler "SETPMOTO" "UNKNOWN" "V1" "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO.quartus_db" { Floorplan "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/" "" "2.671 ns" { GCLK3 fenping:inst|QN[16] } "NODE_NAME" } "" } } { "fenping.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/fenping.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.212 ns) + CELL(1.294 ns) 8.340 ns step_motor:inst1\|clk_scan 3 REG LC_X5_Y3_N9 9 " "Info: 3: + IC(3.212 ns) + CELL(1.294 ns) = 8.340 ns; Loc. = LC_X5_Y3_N9; Fanout = 9; REG Node = 'step_motor:inst1\|clk_scan'" {  } { { "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" "" { Report "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" Compiler "SETPMOTO" "UNKNOWN" "V1" "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO.quartus_db" { Floorplan "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/" "" "4.506 ns" { fenping:inst|QN[16] step_motor:inst1|clk_scan } "NODE_NAME" } "" } } { "step_motor.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/step_motor.vhd" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.290 ns) + CELL(0.918 ns) 12.548 ns step_motor:inst1\|t\[3\] 4 REG LC_X3_Y4_N0 2 " "Info: 4: + IC(3.290 ns) + CELL(0.918 ns) = 12.548 ns; Loc. = LC_X3_Y4_N0; Fanout = 2; REG Node = 'step_motor:inst1\|t\[3\]'" {  } { { "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" "" { Report "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" Compiler "SETPMOTO" "UNKNOWN" "V1" "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO.quartus_db" { Floorplan "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/" "" "4.208 ns" { step_motor:inst1|clk_scan step_motor:inst1|t[3] } "NODE_NAME" } "" } } { "step_motor.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/step_motor.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.669 ns 37.21 % " "Info: Total cell delay = 4.669 ns ( 37.21 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.879 ns 62.79 % " "Info: Total interconnect delay = 7.879 ns ( 62.79 % )" {  } {  } 0}  } { { "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" "" { Report "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" Compiler "SETPMOTO" "UNKNOWN" "V1" "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO.quartus_db" { Floorplan "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/" "" "12.548 ns" { GCLK3 fenping:inst|QN[16] step_motor:inst1|clk_scan step_motor:inst1|t[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "12.548 ns" { GCLK3 GCLK3~combout fenping:inst|QN[16] step_motor:inst1|clk_scan step_motor:inst1|t[3] } { 0.000ns 0.000ns 1.377ns 3.212ns 3.290ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "step_motor.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/step_motor.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.195 ns + Longest register pin " "Info: + Longest register to pin delay is 5.195 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns step_motor:inst1\|t\[3\] 1 REG LC_X3_Y4_N0 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y4_N0; Fanout = 2; REG Node = 'step_motor:inst1\|t\[3\]'" {  } { { "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" "" { Report "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" Compiler "SETPMOTO" "UNKNOWN" "V1" "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO.quartus_db" { Floorplan "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/" "" "" { step_motor:inst1|t[3] } "NODE_NAME" } "" } } { "step_motor.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/step_motor.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.873 ns) + CELL(2.322 ns) 5.195 ns SD\[3\] 2 PIN PIN_55 0 " "Info: 2: + IC(2.873 ns) + CELL(2.322 ns) = 5.195 ns; Loc. = PIN_55; Fanout = 0; PIN Node = 'SD\[3\]'" {  } { { "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" "" { Report "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" Compiler "SETPMOTO" "UNKNOWN" "V1" "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO.quartus_db" { Floorplan "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/" "" "5.195 ns" { step_motor:inst1|t[3] SD[3] } "NODE_NAME" } "" } } { "SETPMOTO.bdf" "" { Schematic "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/SETPMOTO.bdf" { { 160 536 712 176 "SD\[3..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns 44.70 % " "Info: Total cell delay = 2.322 ns ( 44.70 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.873 ns 55.30 % " "Info: Total interconnect delay = 2.873 ns ( 55.30 % )" {  } {  } 0}  } { { "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" "" { Report "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" Compiler "SETPMOTO" "UNKNOWN" "V1" "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO.quartus_db" { Floorplan "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/" "" "5.195 ns" { step_motor:inst1|t[3] SD[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.195 ns" { step_motor:inst1|t[3] SD[3] } { 0.000ns 2.873ns } { 0.000ns 2.322ns } } }  } 0}  } { { "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" "" { Report "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" Compiler "SETPMOTO" "UNKNOWN" "V1" "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO.quartus_db" { Floorplan "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/" "" "12.548 ns" { GCLK3 fenping:inst|QN[16] step_motor:inst1|clk_scan step_motor:inst1|t[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "12.548 ns" { GCLK3 GCLK3~combout fenping:inst|QN[16] step_motor:inst1|clk_scan step_motor:inst1|t[3] } { 0.000ns 0.000ns 1.377ns 3.212ns 3.290ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } } } { "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" "" { Report "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" Compiler "SETPMOTO" "UNKNOWN" "V1" "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO.quartus_db" { Floorplan "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/" "" "5.195 ns" { step_motor:inst1|t[3] SD[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.195 ns" { step_motor:inst1|t[3] SD[3] } { 0.000ns 2.873ns } { 0.000ns 2.322ns } } }  } 0}