setpmoto.fit.qmsg

这是一个用VHDL语言写的电动机程序,希望对大家有用

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version " "Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Oct 21 18:36:05 2006 " "Info: Processing started: Sat Oct 21 18:36:05 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off SETPMOTO -c SETPMOTO " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off SETPMOTO -c SETPMOTO" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "SETPMOTO EPM240T100C5 " "Info: Selected device EPM240T100C5 for design \"SETPMOTO\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Info: Device EPM240T100I5 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Info: Device EPM570T100C5 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Info: Device EPM570T100I5 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1000 MHz " "Info: Assuming a global fmax requirement of 1000 MHz" {  } {  } 0} { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "tsu 2.0 ns " "Info: Assuming a global tsu requirement of 2.0 ns" {  } {  } 0} { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "tco 1.0 ns " "Info: Assuming a global tco requirement of 1.0 ns" {  } {  } 0} { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "tpd 1.0 ns " "Info: Assuming a global tpd requirement of 1.0 ns" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "GCLK3 Global clock in PIN 64 " "Info: Automatically promoted signal \"GCLK3\" to use Global clock in PIN 64" {  } { { "SETPMOTO.bdf" "" { Schematic "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/SETPMOTO.bdf" { { 144 -56 112 160 "GCLK3" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "fenping:inst\|QN\[16\] Global clock " "Info: Automatically promoted some destinations of signal \"fenping:inst\|QN\[16\]\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "fenping:inst\|QN\[16\] " "Info: Destination \"fenping:inst\|QN\[16\]\" may be non-global or may not use global clock" {  } { { "fenping.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/fenping.vhd" 15 -1 0 } }  } 0}  } { { "fenping.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/fenping.vhd" 15 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "step_motor:inst1\|osc Global clock " "Info: Automatically promoted some destinations of signal \"step_motor:inst1\|osc\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "step_motor:inst1\|osc " "Info: Destination \"step_motor:inst1\|osc\" may be non-global or may not use global clock" {  } { { "step_motor.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/step_motor.vhd" 21 -1 0 } }  } 0}  } { { "step_motor.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/step_motor.vhd" 21 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "step_motor:inst1\|clk_scan Global clock " "Info: Automatically promoted some destinations of signal \"step_motor:inst1\|clk_scan\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "step_motor:inst1\|clk_scan " "Info: Destination \"step_motor:inst1\|clk_scan\" may be non-global or may not use global clock" {  } { { "step_motor.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/step_motor.vhd" 17 -1 0 } }  } 0}  } { { "step_motor.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/step_motor.vhd" 17 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Info: Moving registers into LUTs to improve timing and density" {  } {  } 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Info: Started processing fast register assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Info: Finished processing fast register assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "" "Info: Finished moving registers into LUTs" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.666 ns register pin " "Info: Estimated most critical path is register to pin delay of 4.666 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns step_motor:inst1\|t\[3\] 1 REG LAB_X3_Y4 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X3_Y4; Fanout = 2; REG Node = 'step_motor:inst1\|t\[3\]'" {  } { { "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" "" { Report "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" Compiler "SETPMOTO" "UNKNOWN" "V1" "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO.quartus_db" { Floorplan "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/" "" "" { step_motor:inst1|t[3] } "NODE_NAME" } "" } } { "step_motor.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/step_motor.vhd" 19 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.344 ns) + CELL(2.322 ns) 4.666 ns SD\[3\] 2 PIN PIN_55 0 " "Info: 2: + IC(2.344 ns) + CELL(2.322 ns) = 4.666 ns; Loc. = PIN_55; Fanout = 0; PIN Node = 'SD\[3\]'" {  } { { "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" "" { Report "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" Compiler "SETPMOTO" "UNKNOWN" "V1" "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO.quartus_db" { Floorplan "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/" "" "4.666 ns" { step_motor:inst1|t[3] SD[3] } "NODE_NAME" } "" } } { "SETPMOTO.bdf" "" { Schematic "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/SETPMOTO.bdf" { { 160 536 712 176 "SD\[3..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns 49.76 % " "Info: Total cell delay = 2.322 ns ( 49.76 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.344 ns 50.24 % " "Info: Total interconnect delay = 2.344 ns ( 50.24 % )" {  } {  } 0}  } { { "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" "" { Report "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO_cmp.qrpt" Compiler "SETPMOTO" "UNKNOWN" "V1" "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/db/SETPMOTO.quartus_db" { Floorplan "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/" "" "4.666 ns" { step_motor:inst1|t[3] SD[3] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_NOT_USED" "" "Info: Fitter performed an Auto Fit compilation.  No optimizations were skipped because the design's timing and/or routability requirements required full optimization" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Oct 21 18:36:07 2006 " "Info: Processing ended: Sat Oct 21 18:36:07 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}