setpmoto.map.qmsg

这是一个用VHDL语言写的电动机程序,希望对大家有用

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version " "Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Oct 21 18:36:03 2006 " "Info: Processing started: Sat Oct 21 18:36:03 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off SETPMOTO -c SETPMOTO " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off SETPMOTO -c SETPMOTO" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SETPMOTO.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file SETPMOTO.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 SETPMOTO " "Info: Found entity 1: SETPMOTO" {  } { { "SETPMOTO.bdf" "" { Schematic "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/SETPMOTO.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "SETPMOTO " "Info: Elaborating entity \"SETPMOTO\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "step_motor.vhd 2 1 " "Info: Using design file step_motor.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 step_motor-behavior " "Info: Found design unit 1: step_motor-behavior" {  } { { "step_motor.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/step_motor.vhd" 15 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 step_motor " "Info: Found entity 1: step_motor" {  } { { "step_motor.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/step_motor.vhd" 6 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "step_motor step_motor:inst1 " "Info: Elaborating entity \"step_motor\" for hierarchy \"step_motor:inst1\"" {  } { { "SETPMOTO.bdf" "inst1" { Schematic "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/SETPMOTO.bdf" { { 120 376 536 248 "inst1" "" } } } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "keys\[3\] step_motor.vhd(9) " "Warning: Output port \"keys\[3\]\" at step_motor.vhd(9) has no driver" {  } { { "step_motor.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/step_motor.vhd" 9 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "keys\[2\] step_motor.vhd(9) " "Warning: Output port \"keys\[2\]\" at step_motor.vhd(9) has no driver" {  } { { "step_motor.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/step_motor.vhd" 9 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "keys\[1\] step_motor.vhd(9) " "Warning: Output port \"keys\[1\]\" at step_motor.vhd(9) has no driver" {  } { { "step_motor.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/step_motor.vhd" 9 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_OUTPUT_PORT" "keys\[0\] step_motor.vhd(9) " "Warning: Output port \"keys\[0\]\" at step_motor.vhd(9) has no driver" {  } { { "step_motor.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/step_motor.vhd" 9 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "fenping.vhd 2 1 " "Info: Using design file fenping.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fenping-behv " "Info: Found design unit 1: fenping-behv" {  } { { "fenping.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/fenping.vhd" 13 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 fenping " "Info: Found entity 1: fenping" {  } { { "fenping.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/fenping.vhd" 6 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fenping fenping:inst " "Info: Elaborating entity \"fenping\" for hierarchy \"fenping:inst\"" {  } { { "SETPMOTO.bdf" "inst" { Schematic "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/SETPMOTO.bdf" { { 120 112 208 216 "inst" "" } } } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "SET fenping.vhd(20) " "Warning: VHDL Process Statement warning at fenping.vhd(20): signal \"SET\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "fenping.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/SETPMOTO/fenping.vhd" 20 0 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "103 " "Info: Implemented 103 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "5 " "Info: Implemented 5 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "90 " "Info: Implemented 90 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sat Oct 21 18:36:04 2006 " "Info: Processing ended: Sat Oct 21 18:36:04 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}