📄 setpmoto.fit.rpt
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; LAB clocks ; 11 / 32 ( 34 % ) ;
; LUT chains ; 5 / 216 ( 2 % ) ;
; Local interconnects ; 76 / 888 ( 8 % ) ;
; R4s ; 31 / 704 ( 4 % ) ;
+----------------------------+------------------+
+---------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+------------------------------+
; Number of Logic Elements (Average = 6.43) ; Number of LABs (Total = 14) ;
+--------------------------------------------+------------------------------+
; 1 ; 1 ;
; 2 ; 1 ;
; 3 ; 1 ;
; 4 ; 1 ;
; 5 ; 0 ;
; 6 ; 3 ;
; 7 ; 2 ;
; 8 ; 1 ;
; 9 ; 0 ;
; 10 ; 4 ;
+--------------------------------------------+------------------------------+
+-------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+------------------------------+
; LAB-wide Signals (Average = 1.29) ; Number of LABs (Total = 14) ;
+------------------------------------+------------------------------+
; 1 Async. load ; 1 ;
; 1 Clock ; 10 ;
; 1 Clock enable ; 2 ;
; 1 Sync. clear ; 2 ;
; 1 Sync. load ; 1 ;
; 2 Clocks ; 2 ;
+------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+------------------------------+
; Number of Signals Sourced (Average = 5.57) ; Number of LABs (Total = 14) ;
+---------------------------------------------+------------------------------+
; 0 ; 1 ;
; 1 ; 1 ;
; 2 ; 2 ;
; 3 ; 1 ;
; 4 ; 1 ;
; 5 ; 0 ;
; 6 ; 2 ;
; 7 ; 1 ;
; 8 ; 1 ;
; 9 ; 1 ;
; 10 ; 3 ;
+---------------------------------------------+------------------------------+
+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out (Average = 3.21) ; Number of LABs (Total = 14) ;
+-------------------------------------------------+------------------------------+
; 0 ; 1 ;
; 1 ; 4 ;
; 2 ; 2 ;
; 3 ; 2 ;
; 4 ; 1 ;
; 5 ; 0 ;
; 6 ; 3 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 1 ;
+-------------------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+---------------------------------------------+------------------------------+
; Number of Distinct Inputs (Average = 5.64) ; Number of LABs (Total = 14) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 1 ;
; 2 ; 3 ;
; 3 ; 2 ;
; 4 ; 2 ;
; 5 ; 1 ;
; 6 ; 0 ;
; 7 ; 1 ;
; 8 ; 1 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 0 ;
; 12 ; 2 ;
; 13 ; 0 ;
; 14 ; 1 ;
+---------------------------------------------+------------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version
Info: Processing started: Sat Oct 21 18:36:05 2006
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off SETPMOTO -c SETPMOTO
Info: Selected device EPM240T100C5 for design "SETPMOTO"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices.
Info: Device EPM240T100I5 is compatible
Info: Device EPM570T100C5 is compatible
Info: Device EPM570T100I5 is compatible
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1000 MHz
Info: Assuming a global tsu requirement of 2.0 ns
Info: Assuming a global tco requirement of 1.0 ns
Info: Assuming a global tpd requirement of 1.0 ns
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "GCLK3" to use Global clock in PIN 64
Info: Automatically promoted some destinations of signal "fenping:inst|QN[16]" to use Global clock
Info: Destination "fenping:inst|QN[16]" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "step_motor:inst1|osc" to use Global clock
Info: Destination "step_motor:inst1|osc" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "step_motor:inst1|clk_scan" to use Global clock
Info: Destination "step_motor:inst1|clk_scan" may be non-global or may not use global clock
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Moving registers into LUTs to improve timing and density
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished moving registers into LUTs
Info: Finished register packing
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Estimated most critical path is register to pin delay of 4.666 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X3_Y4; Fanout = 2; REG Node = 'step_motor:inst1|t[3]'
Info: 2: + IC(2.344 ns) + CELL(2.322 ns) = 4.666 ns; Loc. = PIN_55; Fanout = 0; PIN Node = 'SD[3]'
Info: Total cell delay = 2.322 ns ( 49.76 % )
Info: Total interconnect delay = 2.344 ns ( 50.24 % )
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Fitter routing operations beginning
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: Fitter performed an Auto Fit compilation. No optimizations were skipped because the design's timing and/or routability requirements required full optimization
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Processing ended: Sat Oct 21 18:36:07 2006
Info: Elapsed time: 00:00:02
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