📄 proj.fit.rpt
字号:
; 3 ; 2 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 3 ;
; 7 ; 2 ;
; 8 ; 1 ;
; 9 ; 1 ;
; 10 ; 10 ;
+--------------------------------------------+------------------------------+
+-------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+------------------------------+
; LAB-wide Signals (Average = 1.42) ; Number of LABs (Total = 19) ;
+------------------------------------+------------------------------+
; 1 Async. clear ; 12 ;
; 1 Clock ; 9 ;
; 1 Clock enable ; 2 ;
; 1 Sync. clear ; 1 ;
; 2 Clocks ; 3 ;
+------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+------------------------------+
; Number of Signals Sourced (Average = 8.53) ; Number of LABs (Total = 19) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 2 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 3 ;
; 7 ; 0 ;
; 8 ; 3 ;
; 9 ; 1 ;
; 10 ; 6 ;
; 11 ; 3 ;
; 12 ; 1 ;
+---------------------------------------------+------------------------------+
+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out (Average = 6.21) ; Number of LABs (Total = 19) ;
+-------------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 1 ;
; 2 ; 0 ;
; 3 ; 3 ;
; 4 ; 2 ;
; 5 ; 2 ;
; 6 ; 0 ;
; 7 ; 4 ;
; 8 ; 2 ;
; 9 ; 4 ;
; 10 ; 1 ;
+-------------------------------------------------+------------------------------+
+-----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+----------------------------------------------+------------------------------+
; Number of Distinct Inputs (Average = 13.00) ; Number of LABs (Total = 19) ;
+----------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 1 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 1 ;
; 7 ; 0 ;
; 8 ; 2 ;
; 9 ; 1 ;
; 10 ; 3 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 1 ;
; 14 ; 2 ;
; 15 ; 0 ;
; 16 ; 1 ;
; 17 ; 2 ;
; 18 ; 3 ;
; 19 ; 1 ;
; 20 ; 1 ;
+----------------------------------------------+------------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version
Info: Processing started: Sat Oct 21 20:52:29 2006
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off LCD_Test -c Proj
Info: Selected device EPM240T100C5 for design "Proj"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices.
Info: Device EPM240T100I5 is compatible
Info: Device EPM570T100C5 is compatible
Info: Device EPM570T100I5 is compatible
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1000 MHz
Info: Assuming a global tsu requirement of 2.0 ns
Info: Assuming a global tco requirement of 1.0 ns
Info: Assuming a global tpd requirement of 1.0 ns
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock in PIN 64
Info: Automatically promoted some destinations of signal "lcd:inst|clk_int" to use Global clock
Info: Destination "lcd:inst|clk_int" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "div16:inst1|count[2]" to use Global clock
Info: Destination "div16:inst1|count[2]" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "lcd:inst|clkdiv" to use Global clock
Info: Destination "lcd:inst|clkdiv" may be non-global or may not use global clock
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Moving registers into LUTs to improve timing and density
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished moving registers into LUTs
Info: Finished register packing
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Estimated most critical path is register to pin delay of 20.304 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X3_Y1; Fanout = 14; REG Node = 'lcd:inst|counter[3]'
Info: 2: + IC(0.903 ns) + CELL(0.914 ns) = 1.817 ns; Loc. = LAB_X2_Y1; Fanout = 1; COMB Node = 'lcd:inst|char_addr~1491'
Info: 3: + IC(0.671 ns) + CELL(0.511 ns) = 2.999 ns; Loc. = LAB_X2_Y1; Fanout = 3; COMB Node = 'lcd:inst|char_addr~1492'
Info: 4: + IC(1.733 ns) + CELL(0.740 ns) = 5.472 ns; Loc. = LAB_X3_Y3; Fanout = 2; COMB Node = 'lcd:inst|char_addr~1494'
Info: 5: + IC(0.982 ns) + CELL(0.200 ns) = 6.654 ns; Loc. = LAB_X3_Y3; Fanout = 5; COMB Node = 'lcd:inst|char_addr[5]~1495'
Info: 6: + IC(1.540 ns) + CELL(0.914 ns) = 9.108 ns; Loc. = LAB_X2_Y1; Fanout = 1; COMB Node = 'lcd:inst|char_addr[5]~1507'
Info: 7: + IC(0.268 ns) + CELL(0.914 ns) = 10.290 ns; Loc. = LAB_X2_Y1; Fanout = 5; COMB Node = 'lcd:inst|char_addr[5]~1509'
Info: 8: + IC(0.671 ns) + CELL(0.511 ns) = 11.472 ns; Loc. = LAB_X2_Y1; Fanout = 3; COMB Node = 'lcd:inst|data~1015'
Info: 9: + IC(2.838 ns) + CELL(0.200 ns) = 14.510 ns; Loc. = LAB_X5_Y3; Fanout = 1; COMB Node = 'lcd:inst|data~1019'
Info: 10: + IC(0.442 ns) + CELL(0.740 ns) = 15.692 ns; Loc. = LAB_X5_Y3; Fanout = 1; COMB Node = 'lcd:inst|data~1020'
Info: 11: + IC(2.290 ns) + CELL(2.322 ns) = 20.304 ns; Loc. = PIN_4; Fanout = 0; PIN Node = 'LCD_D[1]'
Info: Total cell delay = 7.966 ns ( 39.23 % )
Info: Total interconnect delay = 12.338 ns ( 60.77 % )
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Fitter routing operations beginning
Info: Fitter routing operations ending: elapsed time is 00:00:01
Info: Fitter performed an Auto Fit compilation. No optimizations were skipped because the design's timing and/or routability requirements required full optimization
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Processing ended: Sat Oct 21 20:52:32 2006
Info: Elapsed time: 00:00:04
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