📄 seg7disp.fit.rpt
字号:
; fenping:inst1|QN[12] ; 1 ;
; Seg7_Dsp:inst|\Free_Counter:Q[5]~8COUT1_14 ; 1 ;
+--------------------------------------------+---------+
+------------------------------------------------+
; Interconnect Usage Summary ;
+----------------------------+-------------------+
; Interconnect Resource Type ; Usage ;
+----------------------------+-------------------+
; C4s ; 22 / 784 ( 2 % ) ;
; Direct links ; 4 / 888 ( < 1 % ) ;
; Global clocks ; 3 / 4 ( 75 % ) ;
; LAB clocks ; 6 / 32 ( 18 % ) ;
; LUT chains ; 0 / 216 ( 0 % ) ;
; Local interconnects ; 35 / 888 ( 3 % ) ;
; R4s ; 11 / 704 ( 1 % ) ;
+----------------------------+-------------------+
+--------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+-----------------------------+
; Number of Logic Elements (Average = 5.38) ; Number of LABs (Total = 8) ;
+--------------------------------------------+-----------------------------+
; 1 ; 2 ;
; 2 ; 2 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 1 ;
; 9 ; 1 ;
; 10 ; 2 ;
+--------------------------------------------+-----------------------------+
+------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+-----------------------------+
; LAB-wide Signals (Average = 0.63) ; Number of LABs (Total = 8) ;
+------------------------------------+-----------------------------+
; 1 Async. load ; 1 ;
; 1 Clock ; 4 ;
+------------------------------------+-----------------------------+
+---------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+-----------------------------+
; Number of Signals Sourced (Average = 5.38) ; Number of LABs (Total = 8) ;
+---------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 2 ;
; 2 ; 2 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 1 ;
; 9 ; 1 ;
; 10 ; 2 ;
+---------------------------------------------+-----------------------------+
+-------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+-----------------------------+
; Number of Signals Sourced Out (Average = 3.00) ; Number of LABs (Total = 8) ;
+-------------------------------------------------+-----------------------------+
; 0 ; 1 ;
; 1 ; 2 ;
; 2 ; 3 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 2 ;
+-------------------------------------------------+-----------------------------+
+---------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+---------------------------------------------+-----------------------------+
; Number of Distinct Inputs (Average = 2.63) ; Number of LABs (Total = 8) ;
+---------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 1 ;
; 2 ; 3 ;
; 3 ; 2 ;
; 4 ; 2 ;
+---------------------------------------------+-----------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version
Info: Processing started: Sat Oct 21 18:06:50 2006
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off SEG7DISP -c SEG7DISP
Info: Selected device EPM240T100C5 for design "SEG7DISP"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices.
Info: Device EPM240T100I5 is compatible
Info: Device EPM570T100C5 is compatible
Info: Device EPM570T100I5 is compatible
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1000 MHz
Info: Assuming a global tsu requirement of 2.0 ns
Info: Assuming a global tco requirement of 1.0 ns
Info: Assuming a global tpd requirement of 1.0 ns
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "GCLK3" to use Global clock in PIN 64
Info: Automatically promoted some destinations of signal "fenping:inst1|QN[14]" to use Global clock
Info: Destination "fenping:inst1|QN[14]" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "fenping:inst1|QN[15]" to use Global clock
Info: Destination "fenping:inst1|QN[15]" may be non-global or may not use global clock
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Moving registers into LUTs to improve timing and density
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished moving registers into LUTs
Info: Finished register packing
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Estimated most critical path is register to pin delay of 5.508 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X5_Y3; Fanout = 11; REG Node = 'Seg7_Dsp:inst|\Free_Counter:Q[2]'
Info: 2: + IC(0.445 ns) + CELL(0.914 ns) = 1.359 ns; Loc. = LAB_X5_Y3; Fanout = 1; COMB Node = 'b3x8:inst4|YO[0]~118'
Info: 3: + IC(1.827 ns) + CELL(2.322 ns) = 5.508 ns; Loc. = PIN_90; Fanout = 0; PIN Node = 'SEL[6]'
Info: Total cell delay = 3.236 ns ( 58.75 % )
Info: Total interconnect delay = 2.272 ns ( 41.25 % )
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Fitter routing operations beginning
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: Fitter performed an Auto Fit compilation. No optimizations were skipped because the design's timing and/or routability requirements required full optimization
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Processing ended: Sat Oct 21 18:06:51 2006
Info: Elapsed time: 00:00:01
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -