fengping.tan.qmsg

这是一个用VHDL语言写的分频程序,可用得着

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version " "Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Oct 21 21:27:58 2006 " "Info: Processing started: Sat Oct 21 21:27:58 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off FENGPING -c FENGPING " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off FENGPING -c FENGPING" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "GCLK3 " "Info: Assuming node \"GCLK3\" is an undefined clock" {  } { { "FENGPING.bdf" "" { Schematic "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/FENGPING/FENGPING.bdf" { { 104 16 184 120 "GCLK3" "" } } } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "GCLK3" } } } }  } 0}  } {  } 0}