fengping.map.rpt

这是一个用VHDL语言写的分频程序,可用得着

+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                            ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------+
; FENGPING.bdf                     ; yes             ; User Block Diagram/Schematic File  ; E:/EDA/cdrom/mcu_usb_cpld/PLD实验/FENGPING/FENGPING.bdf ;
; fenping.vhd                      ; yes             ; Other                              ; E:/EDA/cdrom/mcu_usb_cpld/PLD实验/FENGPING/fenping.vhd  ;
; fp.vhd                           ; yes             ; Other                              ; E:/EDA/cdrom/mcu_usb_cpld/PLD实验/FENGPING/fp.vhd       ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------+


+---------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary             ;
+-----------------------------------+---------------------+
; Resource                          ; Usage               ;
+-----------------------------------+---------------------+
; Total logic elements              ; 27                  ;
; Total combinational functions     ; 26                  ;
;     -- Total 4-input functions    ; 0                   ;
;     -- Total 3-input functions    ; 2                   ;
;     -- Total 2-input functions    ; 1                   ;
;     -- Total 1-input functions    ; 22                  ;
;     -- Total 0-input functions    ; 1                   ;
; Combinational cells for routing   ; 0                   ;
; Total registers                   ; 26                  ;
; Total logic cells in carry chains ; 22                  ;
; I/O pins                          ; 4                   ;
; Maximum fan-out node              ; fenping:inst|QN[21] ;
; Maximum fan-out                   ; 22                  ;
; Total fan-out                     ; 107                 ;
; Average fan-out                   ; 3.45                ;
+-----------------------------------+---------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                         ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name    ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------------------+
; |FENGPING                  ; 27 (1)      ; 26           ; 0          ; 4    ; 0            ; 1 (1)        ; 1 (0)             ; 25 (0)           ; 22 (0)          ; |FENGPING              ;
;    |fenping:inst|          ; 22 (22)     ; 22           ; 0          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 22 (22)          ; 22 (22)         ; |FENGPING|fenping:inst ;
;    |fp:inst1|              ; 4 (4)       ; 4            ; 0          ; 0    ; 0            ; 0 (0)        ; 1 (1)             ; 3 (3)            ; 0 (0)           ; |FENGPING|fp:inst1     ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 26    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 4     ;
; Number of registers using Asynchronous Load  ; 22    ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; fp:inst1|QN[2]                         ; 3       ;
; fp:inst1|QN[0]                         ; 4       ;
; Total number of inverted registers = 2 ;         ;
+----------------------------------------+---------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/EDA/cdrom/mcu_usb_cpld/PLD实验/FENGPING/FENGPING.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version
    Info: Processing started: Sat Oct 21 21:27:53 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off FENGPING -c FENGPING
Info: Found 1 design units, including 1 entities, in source file FENGPING.bdf
    Info: Found entity 1: FENGPING
Info: Elaborating entity "FENGPING" for the top level hierarchy
Info: Using design file fenping.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: fenping-behv
    Info: Found entity 1: fenping
Info: Elaborating entity "fenping" for hierarchy "fenping:inst"
Warning: VHDL Process Statement warning at fenping.vhd(20): signal "SET" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Using design file fp.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: fp-a
    Info: Found entity 1: fp
Info: Elaborating entity "fp" for hierarchy "fp:inst1"
Warning: VHDL Process Statement warning at fp.vhd(23): signal "SET" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Registers with preset signals will power-up high
Info: Implemented 31 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 3 output pins
    Info: Implemented 27 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Processing ended: Sat Oct 21 21:27:54 2006
    Info: Elapsed time: 00:00:02