fengping.tan.rpt

这是一个用VHDL语言写的分频程序,可用得着

; tco                                                                         ;
+-------+--------------+------------+---------------------+------+------------+
; Slack ; Required tco ; Actual tco ; From                ; To   ; From Clock ;
+-------+--------------+------------+---------------------+------+------------+
; N/A   ; None         ; 11.514 ns  ; fp:inst1|QN[2]      ; LED3 ; GCLK3      ;
; N/A   ; None         ; 8.112 ns   ; fenping:inst|QN[20] ; LED2 ; GCLK3      ;
; N/A   ; None         ; 8.112 ns   ; fenping:inst|QN[20] ; LED0 ; GCLK3      ;
+-------+--------------+------------+---------------------+------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version
    Info: Processing started: Sat Oct 21 21:27:58 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off FENGPING -c FENGPING
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "GCLK3" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "fenping:inst|QN[20]" as buffer
Info: Clock "GCLK3" has Internal fmax of 179.6 MHz between source register "fenping:inst|QN[1]" and destination register "fenping:inst|QN[16]" (period= 5.568 ns)
    Info: + Longest register to register delay is 4.859 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y3_N5; Fanout = 3; REG Node = 'fenping:inst|QN[1]'
        Info: 2: + IC(0.892 ns) + CELL(0.978 ns) = 1.870 ns; Loc. = LC_X2_Y3_N5; Fanout = 2; COMB Node = 'fenping:inst|QN[1]~235'
        Info: 3: + IC(0.000 ns) + CELL(0.123 ns) = 1.993 ns; Loc. = LC_X2_Y3_N6; Fanout = 2; COMB Node = 'fenping:inst|QN[2]~231'
        Info: 4: + IC(0.000 ns) + CELL(0.123 ns) = 2.116 ns; Loc. = LC_X2_Y3_N7; Fanout = 2; COMB Node = 'fenping:inst|QN[3]~227'
        Info: 5: + IC(0.000 ns) + CELL(0.123 ns) = 2.239 ns; Loc. = LC_X2_Y3_N8; Fanout = 2; COMB Node = 'fenping:inst|QN[4]~223'
        Info: 6: + IC(0.000 ns) + CELL(0.399 ns) = 2.638 ns; Loc. = LC_X2_Y3_N9; Fanout = 6; COMB Node = 'fenping:inst|QN[5]~219'
        Info: 7: + IC(0.000 ns) + CELL(0.246 ns) = 2.884 ns; Loc. = LC_X3_Y3_N4; Fanout = 6; COMB Node = 'fenping:inst|QN[10]~199'
        Info: 8: + IC(0.000 ns) + CELL(0.349 ns) = 3.233 ns; Loc. = LC_X3_Y3_N9; Fanout = 6; COMB Node = 'fenping:inst|QN[15]~179'
        Info: 9: + IC(0.000 ns) + CELL(1.626 ns) = 4.859 ns; Loc. = LC_X4_Y3_N0; Fanout = 3; REG Node = 'fenping:inst|QN[16]'
        Info: Total cell delay = 3.967 ns ( 81.64 % )
        Info: Total interconnect delay = 0.892 ns ( 18.36 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "GCLK3" to destination register is 3.458 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_64; Fanout = 22; CLK Node = 'GCLK3'
            Info: 2: + IC(1.377 ns) + CELL(0.918 ns) = 3.458 ns; Loc. = LC_X4_Y3_N0; Fanout = 3; REG Node = 'fenping:inst|QN[16]'
            Info: Total cell delay = 2.081 ns ( 60.18 % )
            Info: Total interconnect delay = 1.377 ns ( 39.82 % )
        Info: - Longest clock path from clock "GCLK3" to source register is 3.458 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_64; Fanout = 22; CLK Node = 'GCLK3'
            Info: 2: + IC(1.377 ns) + CELL(0.918 ns) = 3.458 ns; Loc. = LC_X2_Y3_N5; Fanout = 3; REG Node = 'fenping:inst|QN[1]'
            Info: Total cell delay = 2.081 ns ( 60.18 % )
            Info: Total interconnect delay = 1.377 ns ( 39.82 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Micro setup delay of destination is 0.333 ns
Info: tco from clock "GCLK3" to destination pin "LED3" through register "fp:inst1|QN[2]" is 11.514 ns
    Info: + Longest clock path from clock "GCLK3" to source register is 8.042 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_64; Fanout = 22; CLK Node = 'GCLK3'
        Info: 2: + IC(1.377 ns) + CELL(1.294 ns) = 3.834 ns; Loc. = LC_X4_Y3_N4; Fanout = 8; REG Node = 'fenping:inst|QN[20]'
        Info: 3: + IC(3.290 ns) + CELL(0.918 ns) = 8.042 ns; Loc. = LC_X3_Y4_N0; Fanout = 3; REG Node = 'fp:inst1|QN[2]'
        Info: Total cell delay = 3.375 ns ( 41.97 % )
        Info: Total interconnect delay = 4.667 ns ( 58.03 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Longest register to pin delay is 3.096 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y4_N0; Fanout = 3; REG Node = 'fp:inst1|QN[2]'
        Info: 2: + IC(0.774 ns) + CELL(2.322 ns) = 3.096 ns; Loc. = PIN_97; Fanout = 0; PIN Node = 'LED3'
        Info: Total cell delay = 2.322 ns ( 75.00 % )
        Info: Total interconnect delay = 0.774 ns ( 25.00 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Sat Oct 21 21:27:58 2006
    Info: Elapsed time: 00:00:00