📄 fengping.fit.rpt
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; ~GND ; 1 ;
; fenping:inst|QN[0] ; 1 ;
; fenping:inst|QN[1]~235COUT1_260 ; 1 ;
; fenping:inst|QN[1]~235 ; 1 ;
; fenping:inst|QN[1] ; 1 ;
; fenping:inst|QN[2]~231COUT1_262 ; 1 ;
; fenping:inst|QN[2]~231 ; 1 ;
; fenping:inst|QN[2] ; 1 ;
; fenping:inst|QN[3]~227COUT1_264 ; 1 ;
; fenping:inst|QN[3]~227 ; 1 ;
; fenping:inst|QN[3] ; 1 ;
; fenping:inst|QN[4]~223COUT1_266 ; 1 ;
; fenping:inst|QN[4]~223 ; 1 ;
; fenping:inst|QN[4] ; 1 ;
; fenping:inst|QN[5] ; 1 ;
; fenping:inst|QN[6]~215COUT1_268 ; 1 ;
; fenping:inst|QN[6]~215 ; 1 ;
; fenping:inst|QN[6] ; 1 ;
; fenping:inst|QN[7]~211COUT1_270 ; 1 ;
; fenping:inst|QN[7]~211 ; 1 ;
; fenping:inst|QN[7] ; 1 ;
; fenping:inst|QN[8]~207COUT1_272 ; 1 ;
; fenping:inst|QN[8]~207 ; 1 ;
; fenping:inst|QN[8] ; 1 ;
; fenping:inst|QN[9]~203COUT1_274 ; 1 ;
; fenping:inst|QN[9]~203 ; 1 ;
; fenping:inst|QN[9] ; 1 ;
; fenping:inst|QN[10] ; 1 ;
; fenping:inst|QN[11]~195COUT1_276 ; 1 ;
; fenping:inst|QN[11]~195 ; 1 ;
; fenping:inst|QN[11] ; 1 ;
; fenping:inst|QN[12]~191COUT1_278 ; 1 ;
; fenping:inst|QN[12]~191 ; 1 ;
; fenping:inst|QN[12] ; 1 ;
; fenping:inst|QN[13]~187COUT1_280 ; 1 ;
; fenping:inst|QN[13]~187 ; 1 ;
; fenping:inst|QN[13] ; 1 ;
; fenping:inst|QN[14]~183COUT1_282 ; 1 ;
; fenping:inst|QN[14]~183 ; 1 ;
; fenping:inst|QN[14] ; 1 ;
; fenping:inst|QN[15] ; 1 ;
; fenping:inst|QN[16]~175COUT1_284 ; 1 ;
; fenping:inst|QN[16]~175 ; 1 ;
+----------------------------------+---------+
+------------------------------------------------+
; Interconnect Usage Summary ;
+----------------------------+-------------------+
; Interconnect Resource Type ; Usage ;
+----------------------------+-------------------+
; C4s ; 4 / 784 ( < 1 % ) ;
; Direct links ; 1 / 888 ( < 1 % ) ;
; Global clocks ; 4 / 4 ( 100 % ) ;
; LAB clocks ; 10 / 32 ( 31 % ) ;
; LUT chains ; 0 / 216 ( 0 % ) ;
; Local interconnects ; 10 / 888 ( 1 % ) ;
; R4s ; 2 / 704 ( < 1 % ) ;
+----------------------------+-------------------+
+--------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+-----------------------------+
; Number of Logic Elements (Average = 6.75) ; Number of LABs (Total = 4) ;
+--------------------------------------------+-----------------------------+
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 1 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 2 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 1 ;
+--------------------------------------------+-----------------------------+
+------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+-----------------------------+
; LAB-wide Signals (Average = 1.75) ; Number of LABs (Total = 4) ;
+------------------------------------+-----------------------------+
; 1 Async. clear ; 1 ;
; 1 Async. load ; 2 ;
; 1 Clock ; 3 ;
; 2 Clocks ; 1 ;
+------------------------------------+-----------------------------+
+---------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+-----------------------------+
; Number of Signals Sourced (Average = 6.75) ; Number of LABs (Total = 4) ;
+---------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 1 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 2 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 1 ;
+---------------------------------------------+-----------------------------+
+-------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+-----------------------------+
; Number of Signals Sourced Out (Average = 1.50) ; Number of LABs (Total = 4) ;
+-------------------------------------------------+-----------------------------+
; 0 ; 1 ;
; 1 ; 1 ;
; 2 ; 1 ;
; 3 ; 1 ;
+-------------------------------------------------+-----------------------------+
+---------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+---------------------------------------------+-----------------------------+
; Number of Distinct Inputs (Average = 3.25) ; Number of LABs (Total = 4) ;
+---------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 2 ;
; 3 ; 1 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 1 ;
+---------------------------------------------+-----------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version
Info: Processing started: Sat Oct 21 21:27:55 2006
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off FENGPING -c FENGPING
Info: Selected device EPM240T100C5 for design "FENGPING"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices.
Info: Device EPM240T100I5 is compatible
Info: Device EPM570T100C5 is compatible
Info: Device EPM570T100I5 is compatible
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1000 MHz
Info: Assuming a global tsu requirement of 2.0 ns
Info: Assuming a global tco requirement of 1.0 ns
Info: Assuming a global tpd requirement of 1.0 ns
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "GCLK3" to use Global clock in PIN 64
Info: Automatically promoted some destinations of signal "fenping:inst|QN[20]" to use Global clock
Info: Destination "LED0" may be non-global or may not use global clock
Info: Destination "LED2" may be non-global or may not use global clock
Info: Destination "fenping:inst|QN[20]" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "fenping:inst|QN[21]" to use Global clock
Info: Destination "fenping:inst|QN[21]" may be non-global or may not use global clock
Info: Automatically promoted signal "fp:inst1|QN[3]" to use Global clock
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Moving registers into LUTs to improve timing and density
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished moving registers into LUTs
Info: Finished register packing
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Estimated most critical path is register to pin delay of 2.900 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X3_Y4; Fanout = 3; REG Node = 'fp:inst1|QN[2]'
Info: 2: + IC(0.578 ns) + CELL(2.322 ns) = 2.900 ns; Loc. = PIN_97; Fanout = 0; PIN Node = 'LED3'
Info: Total cell delay = 2.322 ns ( 80.07 % )
Info: Total interconnect delay = 0.578 ns ( 19.93 % )
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Fitter routing operations beginning
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: Fitter performed an Auto Fit compilation. No optimizations were skipped because the design's timing and/or routability requirements required full optimization
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Processing ended: Sat Oct 21 21:27:56 2006
Info: Elapsed time: 00:00:01
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