music.map.qmsg

上个用VHDL语言写的音乐程序,希望对大家能够有帮助

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version " "Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Oct 21 21:18:56 2006 " "Info: Processing started: Sat Oct 21 21:18:56 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off MUSIC -c MUSIC " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off MUSIC -c MUSIC" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "MUSIC.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file MUSIC.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 MUSIC " "Info: Found entity 1: MUSIC" {  } { { "MUSIC.bdf" "" { Schematic "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/MUSIC/MUSIC.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "MUSIC " "Info: Elaborating entity \"MUSIC\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "Songer.vhd 2 1 " "Info: Using design file Songer.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Songer-one " "Info: Found design unit 1: Songer-one" {  } { { "Songer.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/MUSIC/Songer.vhd" 10 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 Songer " "Info: Found entity 1: Songer" {  } { { "Songer.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/MUSIC/Songer.vhd" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Songer Songer:inst1 " "Info: Elaborating entity \"Songer\" for hierarchy \"Songer:inst1\"" {  } { { "MUSIC.bdf" "inst1" { Schematic "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/MUSIC/MUSIC.bdf" { { 120 232 408 216 "inst1" "" } } } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "NoteTabs.vhd 2 1 " "Info: Using design file NoteTabs.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 NoteTabs-one " "Info: Found design unit 1: NoteTabs-one" {  } { { "NoteTabs.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/MUSIC/NoteTabs.vhd" 7 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 NoteTabs " "Info: Found entity 1: NoteTabs" {  } { { "NoteTabs.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/MUSIC/NoteTabs.vhd" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "NoteTabs Songer:inst1\|NoteTabs:u1 " "Info: Elaborating entity \"NoteTabs\" for hierarchy \"Songer:inst1\|NoteTabs:u1\"" {  } { { "Songer.vhd" "u1" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/MUSIC/Songer.vhd" 31 -1 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "Counter NoteTabs.vhd(12) " "Warning: VHDL Process Statement warning at NoteTabs.vhd(12): signal \"Counter\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "NoteTabs.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/MUSIC/NoteTabs.vhd" 12 0 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "NoteTabs.vhd(175) " "Info: VHDL Case Statement information at NoteTabs.vhd(175): OTHERS choice is never selected" {  } { { "NoteTabs.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/MUSIC/NoteTabs.vhd" 175 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "ToneTaba.vhd 2 1 " "Info: Using design file ToneTaba.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ToneTaba-one " "Info: Found design unit 1: ToneTaba-one" {  } { { "ToneTaba.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/MUSIC/ToneTaba.vhd" 9 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 ToneTaba " "Info: Found entity 1: ToneTaba" {  } { { "ToneTaba.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/MUSIC/ToneTaba.vhd" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ToneTaba Songer:inst1\|ToneTaba:u2 " "Info: Elaborating entity \"ToneTaba\" for hierarchy \"Songer:inst1\|ToneTaba:u2\"" {  } { { "Songer.vhd" "u2" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/MUSIC/Songer.vhd" 32 -1 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "HIGH ToneTaba.vhd(11) " "Warning: VHDL Process Statement warning at ToneTaba.vhd(11): signal or variable \"HIGH\" may not be assigned a new value in every possible path through the Process Statement. Signal or variable \"HIGH\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "ToneTaba.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/MUSIC/ToneTaba.vhd" 11 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "Speakera.vhd 2 1 " "Info: Using design file Speakera.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Speakera-one " "Info: Found design unit 1: Speakera-one" {  } { { "Speakera.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/MUSIC/Speakera.vhd" 11 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 Speakera " "Info: Found entity 1: Speakera" {  } { { "Speakera.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/MUSIC/Speakera.vhd" 6 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Speakera Songer:inst1\|Speakera:u3 " "Info: Elaborating entity \"Speakera\" for hierarchy \"Songer:inst1\|Speakera:u3\"" {  } { { "Songer.vhd" "u3" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/MUSIC/Songer.vhd" 33 -1 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "clk1 Speakera.vhd(19) " "Warning: VHDL Process Statement warning at Speakera.vhd(19): signal \"clk1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "Speakera.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/MUSIC/Speakera.vhd" 19 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "fenping.vhd 2 1 " "Info: Using design file fenping.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fenping-behv " "Info: Found design unit 1: fenping-behv" {  } { { "fenping.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/MUSIC/fenping.vhd" 13 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 fenping " "Info: Found entity 1: fenping" {  } { { "fenping.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/MUSIC/fenping.vhd" 6 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fenping fenping:inst " "Info: Elaborating entity \"fenping\" for hierarchy \"fenping:inst\"" {  } { { "MUSIC.bdf" "inst" { Schematic "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/MUSIC/MUSIC.bdf" { { 136 56 152 232 "inst" "" } } } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "SET fenping.vhd(20) " "Warning: VHDL Process Statement warning at fenping.vhd(20): signal \"SET\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "fenping.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/MUSIC/fenping.vhd" 20 0 0 } }  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "Songer:inst1\|Speakera:u3\|SpkS Songer:inst1\|Speakera:u3\|\\DelaySpkS:Count2 " "Info: Duplicate register \"Songer:inst1\|Speakera:u3\|SpkS\" merged to single register \"Songer:inst1\|Speakera:u3\|\\DelaySpkS:Count2\"" {  } { { "Speakera.vhd" "" { Text "E:/EDA/cdrom/mcu_usb_cpld/PLD实验/MUSIC/Speakera.vhd" 9 -1 0 } }  } 0}  } {  } 0}