music.map.rpt

上个用VHDL语言写的音乐程序,希望对大家能够有帮助

+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------------------+
; |MUSIC                     ; 140 (1)     ; 49           ; 0          ; 7    ; 0            ; 91 (1)       ; 8 (0)             ; 41 (0)           ; 41 (0)          ; |MUSIC                          ;
;    |Songer:inst1|          ; 117 (0)     ; 27           ; 0          ; 0    ; 0            ; 90 (0)       ; 8 (0)             ; 19 (0)           ; 19 (0)          ; |MUSIC|Songer:inst1             ;
;       |NoteTabs:u1|        ; 61 (61)     ; 8            ; 0          ; 0    ; 0            ; 53 (53)      ; 0 (0)             ; 8 (8)            ; 8 (8)           ; |MUSIC|Songer:inst1|NoteTabs:u1 ;
;       |Speakera:u3|        ; 26 (26)     ; 19           ; 0          ; 0    ; 0            ; 7 (7)        ; 8 (8)             ; 11 (11)          ; 11 (11)         ; |MUSIC|Songer:inst1|Speakera:u3 ;
;       |ToneTaba:u2|        ; 30 (30)     ; 0            ; 0          ; 0    ; 0            ; 30 (30)      ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |MUSIC|Songer:inst1|ToneTaba:u2 ;
;    |fenping:inst|          ; 22 (22)     ; 22           ; 0          ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 22 (22)          ; 22 (22)         ; |MUSIC|fenping:inst             ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+----------------------------------------------------+
; User-Specified and Inferred Latches                ;
+-----------------------------------------------+----+
; Latch Name                                    ;    ;
+-----------------------------------------------+----+
; Songer:inst1|ToneTaba:u2|HIGH                 ;    ;
; Songer:inst1|ToneTaba:u2|CODE[2]              ;    ;
; Songer:inst1|ToneTaba:u2|CODE[1]              ;    ;
; Songer:inst1|ToneTaba:u2|CODE[0]              ;    ;
; Songer:inst1|ToneTaba:u2|Tone[0]              ;    ;
; Songer:inst1|ToneTaba:u2|Tone[1]              ;    ;
; Songer:inst1|ToneTaba:u2|Tone[2]              ;    ;
; Songer:inst1|ToneTaba:u2|Tone[3]              ;    ;
; Songer:inst1|ToneTaba:u2|Tone[4]              ;    ;
; Songer:inst1|ToneTaba:u2|Tone[5]              ;    ;
; Songer:inst1|ToneTaba:u2|Tone[6]              ;    ;
; Songer:inst1|ToneTaba:u2|Tone[7]              ;    ;
; Songer:inst1|ToneTaba:u2|Tone[8]              ;    ;
; Songer:inst1|ToneTaba:u2|Tone[9]              ;    ;
; Songer:inst1|ToneTaba:u2|Tone[10]             ;    ;
; Number of user-specified and inferred latches ; 15 ;
+-----------------------------------------------+----+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 49    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 11    ;
; Number of registers using Asynchronous Clear ; 14    ;
; Number of registers using Asynchronous Load  ; 22    ;
; Number of registers using Clock Enable       ; 3     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; Songer:inst1|Speakera:u3|QN[0]         ; 2       ;
; Total number of inverted registers = 1 ;         ;
+----------------------------------------+---------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/EDA/cdrom/mcu_usb_cpld/PLD实验/MUSIC/MUSIC.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version
    Info: Processing started: Sat Oct 21 21:18:56 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off MUSIC -c MUSIC
Info: Found 1 design units, including 1 entities, in source file MUSIC.bdf
    Info: Found entity 1: MUSIC
Info: Elaborating entity "MUSIC" for the top level hierarchy
Info: Using design file Songer.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: Songer-one
    Info: Found entity 1: Songer
Info: Elaborating entity "Songer" for hierarchy "Songer:inst1"
Info: Using design file NoteTabs.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: NoteTabs-one
    Info: Found entity 1: NoteTabs
Info: Elaborating entity "NoteTabs" for hierarchy "Songer:inst1|NoteTabs:u1"
Warning: VHDL Process Statement warning at NoteTabs.vhd(12): signal "Counter" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: VHDL Case Statement information at NoteTabs.vhd(175): OTHERS choice is never selected
Info: Using design file ToneTaba.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: ToneTaba-one
    Info: Found entity 1: ToneTaba
Info: Elaborating entity "ToneTaba" for hierarchy "Songer:inst1|ToneTaba:u2"
Warning: VHDL Process Statement warning at ToneTaba.vhd(11): signal or variable "HIGH" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "HIGH" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Using design file Speakera.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: Speakera-one
    Info: Found entity 1: Speakera
Info: Elaborating entity "Speakera" for hierarchy "Songer:inst1|Speakera:u3"
Warning: VHDL Process Statement warning at Speakera.vhd(19): signal "clk1" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Using design file fenping.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: fenping-behv
    Info: Found entity 1: fenping
Info: Elaborating entity "fenping" for hierarchy "fenping:inst"
Warning: VHDL Process Statement warning at fenping.vhd(20): signal "SET" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Duplicate registers merged to single register
    Info: Duplicate register "Songer:inst1|Speakera:u3|SpkS" merged to single register "Songer:inst1|Speakera:u3|\DelaySpkS:Count2"
Warning: Latch Songer:inst1|ToneTaba:u2|HIGH has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal Songer:inst1|NoteTabs:u1|Counter[7]
Warning: Latch Songer:inst1|ToneTaba:u2|CODE[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal Songer:inst1|NoteTabs:u1|ToneIndex[2]
Warning: Latch Songer:inst1|ToneTaba:u2|CODE[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal Songer:inst1|NoteTabs:u1|Counter[7]
Warning: Latch Songer:inst1|ToneTaba:u2|CODE[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal Songer:inst1|NoteTabs:u1|Counter[7]
Warning: Latch Songer:inst1|ToneTaba:u2|Tone[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal Songer:inst1|NoteTabs:u1|Counter[7]
Warning: Latch Songer:inst1|ToneTaba:u2|Tone[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal Songer:inst1|NoteTabs:u1|ToneIndex[2]
Warning: Latch Songer:inst1|ToneTaba:u2|Tone[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal Songer:inst1|NoteTabs:u1|ToneIndex[2]
Warning: Latch Songer:inst1|ToneTaba:u2|Tone[3] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal Songer:inst1|NoteTabs:u1|ToneIndex[2]
Warning: Latch Songer:inst1|ToneTaba:u2|Tone[4] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal Songer:inst1|NoteTabs:u1|ToneIndex[2]
Warning: Latch Songer:inst1|ToneTaba:u2|Tone[5] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal Songer:inst1|NoteTabs:u1|ToneIndex[2]
Warning: Latch Songer:inst1|ToneTaba:u2|Tone[6] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal Songer:inst1|NoteTabs:u1|ToneIndex[2]
Warning: Latch Songer:inst1|ToneTaba:u2|Tone[7] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal Songer:inst1|NoteTabs:u1|ToneIndex[2]
Warning: Latch Songer:inst1|ToneTaba:u2|Tone[8] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal Songer:inst1|NoteTabs:u1|ToneIndex[2]
Warning: Latch Songer:inst1|ToneTaba:u2|Tone[9] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal Songer:inst1|NoteTabs:u1|ToneIndex[2]
Warning: Latch Songer:inst1|ToneTaba:u2|Tone[10] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal Songer:inst1|NoteTabs:u1|ToneIndex[2]
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "led[3]" stuck at GND
Info: Registers with preset signals will power-up high
Info: Implemented 147 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 6 output pins
    Info: Implemented 140 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 36 warnings
    Info: Processing ended: Sat Oct 21 21:19:00 2006
    Info: Elapsed time: 00:00:04