testbench.v

UART_verilog,自己设计的异步串行收发。包括测试文件。

//-This is a testbench of the UART ST16C550-2006211013----//
//------Written by Song Yangjun---------------------------//
//--------------------------------------------------------//
//`include "ST16C550.v"
`timescale 1ns/10ps  
module testbench;
	reg 	RCLK, IOR, IOW_, RESET, RX;
	reg 	[7:0] TX_data;  	//inout D CPU-->FIFO test;
	wire 	[7:0] RX_data;  	//inout D FIFO-->CPU test;
	wire 	[7:0] D;		//inout D
	wire 	DDIS_, INT, TX;
	
	assign D = ( !IOW_ )? TX_data : 8'hzz;	//D is CPU--->FIFO
	assign RX_data = ( IOR )? D : 8'hzz;  	//D is FIFO--->CPU
	
	always #25 RCLK = ~RCLK;
	initial
		begin
		RCLK = 0;
		IOR = 0;
		IOW_ = 1;
		RESET =1;
		RX=1;
		TX_data = 8'hzz;
			
		#200 RESET=0;  		//a reset signal
		#200 RX=0;     		//a start bit
		#800 RX=1;		//1_0_1_0_0_0_1_0  8'hA2
		#800 RX=0;
		#800 RX=1;
		#800 RX=0;
		#800 RX=0;
		#800 RX=0;
		#800 RX=1;
		#800 RX=0;
		#800 RX=0;		//even_odd_parity=0;
		#800 RX=1;		//The end
			 
		#100 IOW_ = 0; TX_data = 8'h52; // 0101_0010 _0
		#50 TX_data = 8'hB4;		// 1011_0100 _1
		#50 TX_data = 8'h27;		// 0010_0111 _1		
		#50 IOW_ = 1; TX_data = 8'hzz;  
				
		#1600 RX=0;		//a start bit
		#800 RX=0;		//0_1_1_0_0_0_1_0;  8'h62
		#800 RX=1;
		#800 RX=1;
		#800 RX=0;
		#800 RX=0;
		#800 RX=0;
		#800 RX=1;
		#800 RX=0;
		#800 RX=0;		//even_odd_parity=0;
		#800 RX=1;		//The end
		#1600 IOR=1;		
		
		#30000 $stop;
		end
	ST16C550 ST16C550 ( .RCLK(RCLK), .IOR(IOR), .IOW_(IOW_), .RESET(RESET), .RX(RX), .D(D), .DDIS_(DDIS_), .INT(INT), .TX(TX) );
endmodule