receive.v

UART_verilog,自己设计的异步串行收发。包括测试文件。

//-------------receive.v-----------Written by Song Yangjun----2006211013-----//
//-------------function: receive data from RX and recode data in the FIFO----//
//-------------and read data from FIFO to CPU--------------------------------//
//-------------When IOR is 1, data is transfered from FIFO to CPU------------//
//-------------and RX is always transfered to FIFO until FIFO is full.-------//
`timescale 1ns/10ps
//`include "FIFO.v"

//--------------------------------------------------------------------------//
module receive( RCLK, RX, RESET, IOR, D, DDIS_, INT );
parameter Idle = 2'b00, Shift = 2'b01, Parity = 2'b10, Stop = 2'b11;
//--------------------------------------------------------------------------//	
	input 	RCLK, RX, RESET, IOR;
	inout 	[7:0] D;
	output 	DDIS_, INT;
	reg 	DDIS_, INT;
	wire 	DDIS_M;
	reg   	rxd1, rxd2;            			//Check the posedge of RX
	reg   	even_odd_flag, flag_buf;   		//flag_buf is for recording the RX's even_odd_bit	
	reg 	[1:0] state;
	reg 	[7:0] Data_In; 
	reg 	reset_reg;				//for reset function
	reg 	[3:0] count;
	reg 	[3:0] bit_counter; 
		
	reg 	FClrN;
	reg 	FInN;
	wire 	[7:0]F_Data;
	wire 	F_FullN;
	wire 	F_EmptyN;
//--------------------------------------------------------------------------//
assign DDIS_M = !DDIS_;
assign D = ( ( IOR && DDIS_M ) && F_EmptyN )? F_Data : 8'hzz;	//DDIS_M -clock
//--------------------------------------------------------------------------//
FIFO FIFO_receive(  .Clk(RCLK),
              .RstN(!RESET),	
              .Data_In(Data_In),
              .FClrN(FClrN),
              .FInN(FInN),
              .FOutN(!(IOR && DDIS_M)),	
              .F_Data(F_Data),
              .F_FullN(F_FullN),
              .F_EmptyN(F_EmptyN)
           );

//--------------------------------------------------------------------------//
always @( posedge RCLK)					//read from RX  in fact shift
if( RESET || reset_reg )
			begin
	FClrN <= 1;
	INT <= 0;
	rxd1 <= 1;
	rxd2 <= 1;
	even_odd_flag <= 1;     			//Signal indicating that FIFO is empty
	flag_buf <= 1;
	state <= 2'b00;
	Data_In[7:0] <= 8'hzz;
	count[3:0] <= 4'h0;
	bit_counter[3:0] <= 4'h0;
	reset_reg <= 0;	
	FInN <= 1;					//jump out reset work.
			end

else    begin 		          			//Receive_task
		rxd1 <= RX;
		rxd2 <= rxd1;      			//judge the negative edge of RX
		count <= count + 1;			
		case( state )
		Idle : begin       			//Check the RX negedge
		       if( !rxd1 && rxd2 ) 
		       		begin
				count <= 0;  		//rvd1 and rvd2 check the negedge RX, and this is a negedge RX
				state <= Idle;   	// Delay 8 periods
				end
		       else if( count[3] && !rxd2 )   	// when RX displays a wrong and short time 0, it could be detected.
		       		begin
				count <= 0; 		//when 8 periods pass, count is reseted.
				state <= Shift;     	//go to shift
				end
		       	    else	state <= Idle;		   
		       end
		Shift : begin      			//transfer the shift_data from RX to Registers but not to CPU
			if ( count == 8 )      
				begin
				if( bit_counter != 8 )  //judge the bits recorded.
					begin
					Data_In[7 - bit_counter] <= rxd2;
					even_odd_flag <= even_odd_flag ^ rxd2;
					bit_counter <= bit_counter + 1;
					state <= Shift;
					end
				else 	begin
					flag_buf <= rxd2;
					state <= Stop;
					end
				end
			else state <= Shift; 		//wait
			end      
		Parity ,
		Stop :	begin     			//Check the EVEN_ODD_bit and decide whether to give out to FIFO.
			if ( count == 8 ) begin
				if( (even_odd_flag == flag_buf) && F_FullN ) FInN <= 0;	 //be not full F_Full=1;
				else begin
				INT <= 1;    		//error --> RX
				FClrN <= 0;		//clear FIFO
				end
				reset_reg <= 1;		//reset
			end
			else state <= Stop;     	//wait;
			 end
		endcase
	end   	

//--------------------------------------------------------------------------//
always @( posedge RCLK)					//read from FIFO to CPU IOR=1 read
begin	if( RESET ) DDIS_ <= 1'b1;
	else    if( IOR || DDIS_M ) begin 		//DDIS_M = !DDIS_
			if( !F_EmptyN ) DDIS_ <= 1;
			else DDIS_ <= 0;
		end		
end
//--------------------------------------------------------------------------//
endmodule