transmit.v

UART_verilog,自己设计的异步串行收发。包括测试文件。

//-----------transmit.v-----------Written by Song Yangjun-----2006211013----//
//-----------function: receive data from CPU and recode data in the FIFO----//
//-----------and read data from FIFO to TX----------------------------------//
//-----------When IOW_ is 0, data from CPU is transfered to FIFO and -------//
//-----------TX will not stop transfering data from FIFO until FIFO is empty//
`timescale 1ns/10ps
//`include "FIFO.v"

//--------------------------------------------------------------------------//
module transmit ( RCLK, IOW_, RESET, D, TX, INT );
	input 	IOW_, RESET, RCLK;
	output 	TX, INT;
	inout	[7:0] D;
	reg	TX;
	reg 	FIFO_TX_OK;			//The reg linked with FIFO.FOutN controls data transfered from FIFO to TX. 0 works
	reg	FIFO_TX_ready;			//FIFO_TX_ready fixes a point to transfer data from FIFO to TX. 1 works.
	reg	even_odd_flag;
	reg	[1:0] state;
	reg 	reset_reg;			//reset job
	reg 	[3:0] count;			
	reg 	[3:0] bit_counter;    		//count how many bits have been transfered 
	reg	[7:0] TX_data;			//TX_data gets data from FIFO.F_data for TX.
	
	wire	INT;				//if there is a error.
	wire 	write_FIFO_ready;		//adjust the time when IOW_ does not have the same step with D. 1 works.
	wire	FClrN;
	wire	[7:0] F_Data;
	wire	F_FullN, F_EmptyN;
	
parameter 	Start = 2'b00, Shift = 2'b01, Parity = 2'b10, Stop = 2'b11;
//--------------------------------------------------------------------------//
assign 	write_FIFO_ready = ( F_FullN )? 1 : 0;	//If FIFO is full, stop
assign 	INT = ( F_FullN )? 0 : 1;				//and give an alarm.
assign	FClrN = 1;
//--------------------------------------------------------------------------//
FIFO FIFO_transmit(  .Clk(RCLK),
              .RstN(!RESET),	
              .Data_In(D),
              .FClrN(FClrN),
              .FInN(!( !IOW_ && write_FIFO_ready )),
              .FOutN(FIFO_TX_OK),	
              .F_Data(F_Data),
              .F_FullN(F_FullN),
              .F_EmptyN(F_EmptyN)
           );

//--------------------------------------------------------------------------//
always @( posedge RCLK )
if( RESET || reset_reg )
			begin
	TX <= 1'b1;
	FIFO_TX_OK <= 1;
	FIFO_TX_ready <= 1;
	even_odd_flag <= 1;
	state <= 2'b00;
	count[3:0] <= 4'h0;
	bit_counter[3:0] <= 4'h0;
	TX_data[7:0] <= 8'hzz;
	reset_reg <= 0;				//jump out reset work.
			end


else begin
	count <= count + 1;			//It is a feedback.
	case( state )
	Start : begin
		if( F_EmptyN ) begin		//F_EmptyN=1 indicates FIFO is not empty.
		FIFO_TX_OK <= 0;		//FOutN = 0 indicaes data is allowed to tansfered to TX.
		TX <= 0;
		count <= 0;
		bit_counter <= 0;
		state <= Shift;
		end
		else state <= Start;
		end
	Shift:	begin
		if( count == 0 && FIFO_TX_ready ) begin  //FIFO_TX_ready =1 initial May be cannot feedback.
		TX_data <= F_Data;
		FIFO_TX_OK <= 1;		//stop transfering data from FIFO to F_Data;
		state <= Shift;
		end
		else if( count == 15 ) begin
			if( bit_counter != 8 ) begin
			FIFO_TX_ready <= 0;		//FIFO_TX_ready closes TX_data's receiving.
			TX <= TX_data[7 - bit_counter];
			even_odd_flag <= even_odd_flag ^TX_data[7 - bit_counter];
			bit_counter <= bit_counter + 1;         
			state <= Shift;
			end
			else begin
			TX <= even_odd_flag;
			state <= Stop;
			end
		     end
		     else state <= Shift;
		end
	Parity,
	Stop:	begin
		if( count == 15 ) 
			if( bit_counter == 8 ) begin	//delay stop flag
			TX <= 1;			//stop flag
			bit_counter <= bit_counter + 1;
			end
			else	reset_reg <= 1;
		else state <= Stop;
		end
	endcase
     end

//--------------------------------------------------------------------------//
endmodule