📄 iolm3s811.h
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/* UART Control (UARTCTL) */
typedef struct {
__REG32 UARTEN : 1;
__REG32 : 6;
__REG32 LBE : 1;
__REG32 TXE : 1;
__REG32 RXE : 1;
__REG32 :22;
} __uartctl_bits;
/* UART Interrupt FIFO Level Select (UARTIFLS) */
typedef struct {
__REG32 TXIFLSEL : 3;
__REG32 RXIFLSEL : 3;
__REG32 :26;
} __uartifls_bits;
/* UART Interrupt Mask (UARTIM) */
typedef struct {
__REG32 : 4;
__REG32 RXIM : 1;
__REG32 TXIM : 1;
__REG32 RTIM : 1;
__REG32 FEIM : 1;
__REG32 PEIM : 1;
__REG32 BEIM : 1;
__REG32 OEIM : 1;
__REG32 :21;
} __uartim_bits;
/* UART Raw Interrupt Status (UARTRIS) */
typedef struct {
__REG32 : 4;
__REG32 RXRIS : 1;
__REG32 TXRIS : 1;
__REG32 RTRIS : 1;
__REG32 FERIS : 1;
__REG32 PERIS : 1;
__REG32 BERIS : 1;
__REG32 OERIS : 1;
__REG32 :21;
} __uartris_bits;
/* UART Masked Interrupt Status (UARTMIS) */
typedef struct {
__REG32 : 4;
__REG32 RXMIS : 1;
__REG32 TXMIS : 1;
__REG32 RTMIS : 1;
__REG32 FEMIS : 1;
__REG32 PEMIS : 1;
__REG32 BEMIS : 1;
__REG32 OEMIS : 1;
__REG32 :21;
} __uartmis_bits;
/* UART Interrupt Clear (UARTICR) */
typedef struct {
__REG32 : 4;
__REG32 RXIC : 1;
__REG32 TXIC : 1;
__REG32 RTIC : 1;
__REG32 FEIC : 1;
__REG32 PEIC : 1;
__REG32 BEIC : 1;
__REG32 OEIC : 1;
__REG32 :21;
} __uarticr_bits;
/* SSI Control 0 (SSICR0) */
typedef struct {
__REG32 DSS : 4;
__REG32 FRF : 2;
__REG32 SPO : 1;
__REG32 SPH : 1;
__REG32 SCR : 8;
__REG32 :16;
} __ssicr0_bits;
/* SSI Control 1 (SSICR1) */
typedef struct {
__REG32 LBM : 1;
__REG32 SSE : 1;
__REG32 MS : 1;
__REG32 SOD : 1;
__REG32 :28;
} __ssicr1_bits;
/* SSI Status (SSISR) */
typedef struct {
__REG32 TFE : 1;
__REG32 TNF : 1;
__REG32 RNE : 1;
__REG32 RFF : 1;
__REG32 BSY : 1;
__REG32 :27;
} __ssisr_bits;
/* SSI Interrupt Mask (SSIIM) */
typedef struct {
__REG32 RORIM : 1;
__REG32 RTIM : 1;
__REG32 RXIM : 1;
__REG32 TXIM : 1;
__REG32 :28;
} __ssiim_bits;
/* SSI Raw Interrupt Status (SSIRIS) */
typedef struct {
__REG32 RORRIS : 1;
__REG32 RTRIS : 1;
__REG32 RXRIS : 1;
__REG32 TXRIS : 1;
__REG32 :28;
} __ssiris_bits;
/* SSI Masked Interrupt Status (SSIMIS) */
typedef struct {
__REG32 RORMIS : 1;
__REG32 RTMIS : 1;
__REG32 RXMIS : 1;
__REG32 TXMIS : 1;
__REG32 :28;
} __ssimis_bits;
/* SSI Interrupt Clear (SSIICR) */
typedef struct {
__REG32 RORIC : 1;
__REG32 RTIC : 1;
__REG32 :30;
} __ssiicr_bits;
/* I2C Master Slave Address (I2CMSA) */
typedef struct {
__REG32 R_S : 1;
__REG32 SA : 7;
__REG32 :24;
} __i2cmsa_bits;
/* I2C Master Control/Status (I2CMCS) */
typedef union {
/* I2CMS */
struct {
__REG32 BUSY : 1;
__REG32 ERROR : 1;
__REG32 ADRACK : 1;
__REG32 DATACK : 1;
__REG32 ARBLST : 1;
__REG32 IDLE : 1;
__REG32 BUSBSY : 1;
__REG32 :25;
};
/* I2CMC */
struct {
__REG32 RUN : 1;
__REG32 START : 1;
__REG32 STOP : 1;
__REG32 ACK : 1;
__REG32 :28;
};
} __i2cmcs_bits;
/* I2C Master Interrupt Mask (I2CMIMR) */
typedef struct {
__REG32 IM : 1;
__REG32 :31;
} __i2cmimr_bits;
/* I2C Master Raw Interrupt Status (I2CMRIS) */
typedef struct {
__REG32 RIS : 1;
__REG32 :31;
} __i2cmris_bits;
/* I2C Master Masked Interrupt Status (I2CMMIS) */
typedef struct {
__REG32 MIS : 1;
__REG32 :31;
} __i2cmmis_bits;
/* I2C Master Interrupt Clear (I2CMICR) */
typedef struct {
__REG32 IC : 1;
__REG32 :31;
} __i2cmicr_bits;
/* I2C Master Configuration (I2CMCR) */
typedef struct {
__REG32 LPBK : 1;
__REG32 : 3;
__REG32 MFE : 1;
__REG32 SFE : 1;
__REG32 :26;
} __i2cmcr_bits;
/* I2C Slave Own Address (I2CSOAR) */
typedef struct {
__REG32 OAR : 7;
__REG32 :25;
} __i2csoar_bits;
/* I2C Slave Control/Status (I2CSCSR) */
typedef union {
/* I2CSSR */
struct {
__REG32 RREQ : 1;
__REG32 TREQ : 1;
__REG32 :30;
};
/* I2CSCR */
struct {
__REG32 DA : 1;
__REG32 :31;
};
} __i2cscsr_bits;
/* I2C Slave Interrupt Mask (I2CSIMR) */
typedef struct {
__REG32 IM : 1;
__REG32 :31;
} __i2csimr_bits;
/* I2C Slave Raw Interrupt Status (I2CSRIS) */
typedef struct {
__REG32 RIS : 1;
__REG32 :31;
} __i2csris_bits;
/* I2C Slave Masked Interrupt Status (I2CSMIS) */
typedef struct {
__REG32 MIS : 1;
__REG32 :31;
} __i2csmis_bits;
/* I2C Slave Interrupt Clear (I2CSICR) */
typedef struct {
__REG32 IC : 1;
__REG32 :31;
} __i2csicr_bits;
/* Analog Comparator Masked Interrupt Status (ACMIS)
Analog Comparator Raw Interrupt Status (ACRIS)
Analog Comparator Interrupt Enable (ACINTEN) */
typedef struct {
__REG32 IN0 : 1;
__REG32 :31;
} __acmis_bits;
/* Analog Comparator Reference Voltage Control (ACREFCTL) */
typedef struct {
__REG32 VREF : 4;
__REG32 : 4;
__REG32 RNG : 1;
__REG32 EN : 1;
__REG32 :22;
} __acrefctl_bits;
/* Analog Comparator Status (ACSTAT) */
typedef struct {
__REG32 : 1;
__REG32 OVAL : 1;
__REG32 :30;
} __acstat_bits;
/* Analog Comparator Control (ACCTL) */
typedef struct {
__REG32 : 1;
__REG32 CINV : 1;
__REG32 ISEN : 2;
__REG32 ISLVAL : 1;
__REG32 : 4;
__REG32 ASRCP : 2;
__REG32 :21;
} __acctl_bits;
/* Pulse Width Modulator Master Control (PWMCTL) */
typedef struct {
__REG32 GlobalSync0 : 1;
__REG32 GlobalSync1 : 1;
__REG32 :30;
} __pwmctl_bits;
/* Pulse Width Modulator Time Base Sync (PWMSYNC) */
typedef struct {
__REG32 Sync0 : 1;
__REG32 Sync1 : 1;
__REG32 :30;
} __pwmsync_bits;
/* Pulse Width Modulator Output Enable (PWMENABLE) */
typedef struct {
__REG32 PWM0En : 1;
__REG32 PWM1En : 1;
__REG32 PWM2En : 1;
__REG32 PWM3En : 1;
__REG32 :28;
} __pwmenable_bits;
/* Pulse Width Modulator Output Inversion (PWMINVERT) */
typedef struct {
__REG32 PWM0Inv : 1;
__REG32 PWM1Inv : 1;
__REG32 PWM2Inv : 1;
__REG32 PWM3Inv : 1;
__REG32 :28;
} __pwminvert_bits;
/* Pulse Width Modulator Output Fault (PWMFAULT) */
typedef struct {
__REG32 Fault0 : 1;
__REG32 Fault1 : 1;
__REG32 Fault2 : 1;
__REG32 Fault3 : 1;
__REG32 :28;
} __pwmfault_bits;
/* Pulse Width Modulator Interrupt Enable (PWMINTEN) */
typedef struct {
__REG32 IntPWM0 : 1;
__REG32 IntPWM1 : 1;
__REG32 :14;
__REG32 IntFault : 1;
__REG32 :15;
} __pwminten_bits;
/* Pulse Width Modulator Interrupt Status (PWMRIS) */
typedef struct {
__REG32 IntPWM0 : 1;
__REG32 IntPWM1 : 1;
__REG32 :14;
__REG32 IntFault : 1;
__REG32 :15;
} __pwmris_bits;
/* Pulse Width Modulator Interrupt Status and Clear (PWMISC) */
typedef struct {
__REG32 IntPWM0 : 1;
__REG32 IntPWM1 : 1;
__REG32 :14;
__REG32 IntFault : 1;
__REG32 :15;
} __pwmisc_bits;
/* Pulse Width Modulator Status (PWMSTATUS) */
typedef struct {
__REG32 Fault : 1;
__REG32 :31;
} __pwmstatus_bits;
/* Pulse Width Modulator 0 Control (PWM0CTL) */
typedef struct {
__REG32 Enable : 1;
__REG32 Mode : 1;
__REG32 Debug : 1;
__REG32 LoadUpd : 1;
__REG32 CmpAUpd : 1;
__REG32 CmpBUpd : 1;
__REG32 :26;
} __pwm0ctl_bits;
/* Pulse Width Modulator 0 Interrupt/Trigger Enable (PWM0INTEN) */
typedef struct {
__REG32 IntCntZero : 1;
__REG32 IntCntLoad : 1;
__REG32 IntCmpAU : 1;
__REG32 IntCmpAD : 1;
__REG32 IntCmpBU : 1;
__REG32 IntCmpBD : 1;
__REG32 : 2;
__REG32 TrCntZero : 1;
__REG32 TrCntLoad : 1;
__REG32 TrCmpAU : 1;
__REG32 TrCmpAD : 1;
__REG32 TrCmpBU : 1;
__REG32 TrCmpBD : 1;
__REG32 :18;
} __pwm0inten_bits;
/* Pulse Width Modulator 0 Raw Interrupt Status (PWM0RIS) */
typedef struct {
__REG32 IntCntZero : 1;
__REG32 IntCntLoad : 1;
__REG32 IntCmpAU : 1;
__REG32 IntCmpAD : 1;
__REG32 IntCmpBU : 1;
__REG32 IntCmpBD : 1;
__REG32 :26;
} __pwm0ris_bits;
/* Pulse Width Modulator 0 Interrupt Status and Clear (PWM0ISC) */
typedef struct {
__REG32 IntCntZero : 1;
__REG32 IntCntLoad : 1;
__REG32 IntCmpAU : 1;
__REG32 IntCmpAD : 1;
__REG32 IntCmpBU : 1;
__REG32 IntCmpBD : 1;
__REG32 :26;
} __pwm0isc_bits;
/* Pulse Width Modulator 0 Load (PWM0LOAD) */
typedef struct {
__REG32 Load :16;
__REG32 :16;
} __pwm0load_bits;
/* Pulse Width Modulator 0 Counter (PWM0COUNT) */
typedef struct {
__REG32 Count :16;
__REG32 :16;
} __pwm0count_bits;
/* Pulse Width Modulator 0 Compare A (PWM0CMPA) */
typedef struct {
__REG32 CompA :16;
__REG32 :16;
} __pwm0cmpa_bits;
/* Pulse Width Modulator 0 Compare B (PWM0CMPB) */
typedef struct {
__REG32 CompB :16;
__REG32 :16;
} __pwm0cmpb_bits;
/* Pulse Width Modulator 0 Generator A Control (PWM0GENA) */
typedef struct {
__REG32 ActZer0 : 2;
__REG32 ActLoad : 2;
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