📄 iolm3s811.h
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__REG32 :21;
} __gptmimr_bits;
/* GPTM Raw Interrupt Status (GPTMRIS) */
typedef struct {
__REG32 TATORIS : 1;
__REG32 C1MRIS : 1;
__REG32 C1ERIS : 1;
__REG32 RTCRIS : 1;
__REG32 : 4;
__REG32 TBTORIS : 1;
__REG32 C2MRIS : 1;
__REG32 C2ERIS : 1;
__REG32 :21;
} __gptmris_bits;
/* GPTM Masked Interrupt Status (GPTMMIS) */
typedef struct {
__REG32 TATOMIS : 1;
__REG32 C1MMIS : 1;
__REG32 C1EMIS : 1;
__REG32 RTCMIS : 1;
__REG32 : 4;
__REG32 TBTOMIS : 1;
__REG32 C2MMIS : 1;
__REG32 C2EMIS : 1;
__REG32 :21;
} __gptmmis_bits;
/* GPTM Interrupt Clear (GPTMICR) */
typedef struct {
__REG32 TATOCINT : 1;
__REG32 C1MCINT : 1;
__REG32 C1ECINT : 1;
__REG32 RTCCINT : 1;
__REG32 : 4;
__REG32 TBTOCINT : 1;
__REG32 C2MCINT : 1;
__REG32 C2ECINT : 1;
__REG32 :21;
} __gptmicr_bits;
/* GPTM TimerA Interval Load (GPTMTAILR) */
typedef struct {
__REG32 TAILRL :16;
__REG32 TAILRH :16;
} __gptmtailr_bits;
/* GPTM TimerA Match (GPTMTAMATCHR) */
typedef struct {
__REG32 TAMRL :16;
__REG32 TAMRH :16;
} __gptmtamatchr_bits;
/* GPTM TimerA (GPTMTAR) */
typedef struct {
__REG32 TARL :16;
__REG32 TARH :16;
} __gptmtar_bits;
/* Watchdog Control (WDTCTL) */
typedef struct {
__REG32 INTEN : 1;
__REG32 RESEN : 1;
__REG32 :30;
} __wdtctl_bits;
/* Watchdog Raw Interrupt Status (WDTRIS) */
typedef struct {
__REG32 WDTRIS : 1;
__REG32 :31;
} __wdtris_bits;
/* Watchdog Masked Interrupt Status (WDTMIS) */
typedef struct {
__REG32 WDTMIS : 1;
__REG32 :31;
} __wdtmis_bits;
/* Analog-to-Digital Converter Active Sample Sequencer (ADCACTSS) */
typedef struct {
__REG32 ASEN0 : 1;
__REG32 ASEN1 : 1;
__REG32 ASEN2 : 1;
__REG32 ASEN3 : 1;
__REG32 :28;
} __adcactss_bits;
/* Analog-to-Digital Converter Raw Interrupt Status (ADCRIS) */
typedef struct {
__REG32 INR0 : 1;
__REG32 INR1 : 1;
__REG32 INR2 : 1;
__REG32 INR3 : 1;
__REG32 :28;
} __adcris_bits;
/* Analog-to-Digital Converter Interrupt Mask (ADCIM) */
typedef struct {
__REG32 MASK0 : 1;
__REG32 MASK1 : 1;
__REG32 MASK2 : 1;
__REG32 MASK3 : 1;
__REG32 :28;
} __adcim_bits;
/* Analog-to-Digital Converter Interrupt Status and Clear (ADCISC) */
typedef struct {
__REG32 IN0 : 1;
__REG32 IN1 : 1;
__REG32 IN2 : 1;
__REG32 IN3 : 1;
__REG32 :28;
} __adcisc_bits;
/* Analog-to-Digital Converter Overflow Status (ADCOSTAT) */
typedef struct {
__REG32 OV0 : 1;
__REG32 OV1 : 1;
__REG32 OV2 : 1;
__REG32 OV3 : 1;
__REG32 :28;
} __adcostat_bits;
/* Analog-to-Digital Converter Event Multiplexer Select (ADCEMUX) */
typedef struct {
__REG32 EM0 : 4;
__REG32 EM1 : 4;
__REG32 EM2 : 4;
__REG32 EM3 : 4;
__REG32 :16;
} __adcemux_bits;
/* Analog-to-Digital Converter Underflow Status (ADCUSTAT) */
typedef struct {
__REG32 UV0 : 1;
__REG32 UV1 : 1;
__REG32 UV2 : 1;
__REG32 UV3 : 1;
__REG32 :28;
} __adcustat_bits;
/* Analog-to-Digital Converter Sample Sequencer Priority (ADCSSPRI) */
typedef struct {
__REG32 SS0 : 2;
__REG32 : 2;
__REG32 SS1 : 2;
__REG32 : 2;
__REG32 SS2 : 2;
__REG32 : 2;
__REG32 SS3 : 2;
__REG32 :18;
} __adcsspri_bits;
/* Analog-to-Digital Converter Processor Sample Sequence Initiate (ADCPSSI) */
typedef struct {
__REG32 SS0 : 1;
__REG32 SS1 : 1;
__REG32 SS2 : 1;
__REG32 SS3 : 1;
__REG32 :28;
} __adcpssi_bits;
/* Analog-to-Digital Converter Sample Sequence Input Mux Select 0 (ADCSSMUX0) */
typedef struct {
__REG32 MUX0 : 2;
__REG32 : 2;
__REG32 MUX1 : 2;
__REG32 : 2;
__REG32 MUX2 : 2;
__REG32 : 2;
__REG32 MUX3 : 2;
__REG32 : 2;
__REG32 MUX4 : 2;
__REG32 : 2;
__REG32 MUX5 : 2;
__REG32 : 2;
__REG32 MUX6 : 2;
__REG32 : 2;
__REG32 MUX7 : 2;
__REG32 : 2;
} __adcssmux0_bits;
/* Analog-to-Digital Converter Sample Sequence Control 0 (ADCSSCTL0) */
typedef struct {
__REG32 D0 : 1;
__REG32 END0 : 1;
__REG32 IE0 : 1;
__REG32 TS0 : 1;
__REG32 D1 : 1;
__REG32 END1 : 1;
__REG32 IE1 : 1;
__REG32 TS1 : 1;
__REG32 D2 : 1;
__REG32 END2 : 1;
__REG32 IE2 : 1;
__REG32 TS2 : 1;
__REG32 D3 : 1;
__REG32 END3 : 1;
__REG32 IE3 : 1;
__REG32 TS3 : 1;
__REG32 D4 : 1;
__REG32 END4 : 1;
__REG32 IE4 : 1;
__REG32 TS4 : 1;
__REG32 D5 : 1;
__REG32 END5 : 1;
__REG32 IE5 : 1;
__REG32 TS5 : 1;
__REG32 D6 : 1;
__REG32 END6 : 1;
__REG32 IE6 : 1;
__REG32 TS6 : 1;
__REG32 D7 : 1;
__REG32 END7 : 1;
__REG32 IE7 : 1;
__REG32 TS7 : 1;
} __adcssctl0_bits;
/* Analog-to-Digital Converter Sample Sequence FIFO 0 (ADCSSFIFO0) */
typedef struct {
__REG32 DATA :10;
__REG32 :22;
} __adcssfifo0_bits;
/* Analog-to-Digital Converter Sample Sequence FIFO 0 Status (ADCSSFSTAT0) */
typedef struct {
__REG32 TPTR : 4;
__REG32 HPTR : 4;
__REG32 EMPTY : 1;
__REG32 : 3;
__REG32 FULL : 1;
__REG32 :19;
} __adcssfstat0_bits;
/* Analog-to-Digital Converter Sample Sequence Input Mux Select 1 (ADCSSMUX1) */
typedef struct {
__REG32 MUX0 : 2;
__REG32 : 2;
__REG32 MUX1 : 2;
__REG32 : 2;
__REG32 MUX2 : 2;
__REG32 : 2;
__REG32 MUX3 : 2;
__REG32 :18;
} __adcssmux1_bits;
/* Analog-to-Digital Converter Sample Sequence Control 1 (ADCSSCTL1) */
typedef struct {
__REG32 D0 : 1;
__REG32 END0 : 1;
__REG32 IE0 : 1;
__REG32 TS0 : 1;
__REG32 D1 : 1;
__REG32 END1 : 1;
__REG32 IE1 : 1;
__REG32 TS1 : 1;
__REG32 D2 : 1;
__REG32 END2 : 1;
__REG32 IE2 : 1;
__REG32 TS2 : 1;
__REG32 D3 : 1;
__REG32 END3 : 1;
__REG32 IE3 : 1;
__REG32 TS3 : 1;
__REG32 :16;
} __adcssctl1_bits;
/* Analog-to-Digital Converter Sample Sequence FIFO 1 (ADCSSFIFO1) */
typedef struct {
__REG32 DATA :10;
__REG32 :22;
} __adcssfifo1_bits;
/* Analog-to-Digital Converter Sample Sequence FIFO 1 Status (ADCSSFSTAT1) */
typedef struct {
__REG32 TPTR : 4;
__REG32 HPTR : 4;
__REG32 EMPTY : 1;
__REG32 : 3;
__REG32 FULL : 1;
__REG32 :19;
} __adcssfstat1_bits;
/* Analog-to-Digital Converter Sample Sequence Input Mux Select 2 (ADCSSMUX2) */
typedef struct {
__REG32 MUX0 : 2;
__REG32 : 2;
__REG32 MUX1 : 2;
__REG32 : 2;
__REG32 MUX2 : 2;
__REG32 : 2;
__REG32 MUX3 : 2;
__REG32 :18;
} __adcssmux2_bits;
/* Analog-to-Digital Converter Sample Sequence Control 2 (ADCSSCTL2) */
typedef struct {
__REG32 D0 : 1;
__REG32 END0 : 1;
__REG32 IE0 : 1;
__REG32 TS0 : 1;
__REG32 D1 : 1;
__REG32 END1 : 1;
__REG32 IE1 : 1;
__REG32 TS1 : 1;
__REG32 D2 : 1;
__REG32 END2 : 1;
__REG32 IE2 : 1;
__REG32 TS2 : 1;
__REG32 D3 : 1;
__REG32 END3 : 1;
__REG32 IE3 : 1;
__REG32 TS3 : 1;
__REG32 :16;
} __adcssctl2_bits;
/* Analog-to-Digital Converter Sample Sequence FIFO 2 (ADCSSFIFO2) */
typedef struct {
__REG32 DATA :10;
__REG32 :22;
} __adcssfifo2_bits;
/* Analog-to-Digital Converter Sample Sequence FIFO 2 Status (ADCSSFSTAT2) */
typedef struct {
__REG32 TPTR : 4;
__REG32 HPTR : 4;
__REG32 EMPTY : 1;
__REG32 : 3;
__REG32 FULL : 1;
__REG32 :19;
} __adcssfstat2_bits;
/* Analog-to-Digital Converter Sample Sequence Input Mux Select 3 (ADCSSMUX3) */
typedef struct {
__REG32 MUX0 : 2;
__REG32 :30;
} __adcssmux3_bits;
/* Analog-to-Digital Converter Sample Sequence Control 3 (ADCSSCTL3) */
typedef struct {
__REG32 D0 : 1;
__REG32 END0 : 1;
__REG32 IE0 : 1;
__REG32 TS0 : 1;
__REG32 :28;
} __adcssctl3_bits;
/* Analog-to-Digital Converter Sample Sequence FIFO 3 (ADCSSFIFO3) */
typedef struct {
__REG32 DATA :10;
__REG32 :22;
} __adcssfifo3_bits;
/* Analog-to-Digital Converter Sample Sequence FIFO 3 Status (ADCSSFSTAT3) */
typedef struct {
__REG32 TPTR : 4;
__REG32 HPTR : 4;
__REG32 EMPTY : 1;
__REG32 : 3;
__REG32 FULL : 1;
__REG32 :19;
} __adcssfstat3_bits;
/* Analog-to-Digital Converter Test Mode Loopback (ADCTMLB) */
typedef struct {
__REG32 MUX : 3;
__REG32 TS : 1;
__REG32 DIFF : 1;
__REG32 CONT : 1;
__REG32 CNT : 4;
__REG32 :22;
} __adctmlb_bits;
/* UART Data (UARTDR) */
typedef struct {
__REG32 DATA : 8;
__REG32 FE : 1;
__REG32 PE : 1;
__REG32 BE : 1;
__REG32 OE : 1;
__REG32 :20;
} __uartdr_bits;
/* UART Receive Status/Error Clear (UARTRSR/UARTECR) */
typedef union {
/* UARTRSR */
struct {
__REG32 FE : 1;
__REG32 PE : 1;
__REG32 BE : 1;
__REG32 OE : 1;
__REG32 :28;
};
/* UARTECR */
struct {
__REG32 DATA : 8;
__REG32 :24;
};
} __uartrsr_bits;
/* UART Flag (UARTFR) */
typedef struct {
__REG32 : 3;
__REG32 BUSY : 1;
__REG32 RXFE : 1;
__REG32 TXFF : 1;
__REG32 RXFF : 1;
__REG32 TXFE : 1;
__REG32 :24;
} __uartfr_bits;
/* UART Fractional Baud-Rate Divisor (UARTFBRD) */
typedef struct {
__REG32 DIVFRAC : 6;
__REG32 :26;
} __uartfbrd_bits;
/* UART Line Control (UARTLCRH) */
typedef struct {
__REG32 BRK : 1;
__REG32 PEN : 1;
__REG32 EPS : 1;
__REG32 STP2 : 1;
__REG32 FEN : 1;
__REG32 WLEN : 2;
__REG32 SPS : 1;
__REG32 :24;
} __uartlcrh_bits;
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