📄 iolm3s811.h
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/***************************************************************************
**
** This file defines the Special Function Registers for
** Luminary LM3S811
**
** Used with ARM IAR C/C++ Compiler and Assembler
**
** (c) Copyright IAR Systems 2006
**
** $Revision: 1.1.2.4 $
**
***************************************************************************/
#ifndef __IOLM3S811_H
#define __IOLM3S811_H
#if (((__TID__ >> 8) & 0x7F) != 0x4F)
#error This file should only be compiled by ARM IAR compiler and assembler
#endif
#include "io_macros.h"
/***************************************************************************
***************************************************************************
**
** LM3S811 SPECIAL FUNCTION REGISTERS
**
***************************************************************************
***************************************************************************
***************************************************************************/
/* C-compiler specific declarations ***************************************/
#ifdef __IAR_SYSTEMS_ICC__
#ifndef _SYSTEM_BUILD
#pragma system_include
#endif
/* Device Identification 0 (DID0) */
typedef struct {
__REG32 MINOR : 8;
__REG32 MAJOR : 8;
__REG32 :12;
__REG32 VER : 3;
__REG32 : 1;
} __did0_bits;
/* Device Identification 1 (DID1) */
typedef struct {
__REG32 QUAL : 2;
__REG32 ROHS : 1;
__REG32 PKG : 2;
__REG32 TEMP : 3;
__REG32 : 8;
__REG32 PARTNO : 8;
__REG32 FAM : 4;
__REG32 VER : 4;
} __did1_bits;
/* Device Capabilities 0 (DC0) */
typedef struct {
__REG32 FLSHSZ :16;
__REG32 SRAMSZ :16;
} __dc0_bits;
/* Device Capabilities 1 (DC1) */
typedef struct {
__REG32 JTAG : 1;
__REG32 SWD : 1;
__REG32 SWO : 1;
__REG32 WDT : 1;
__REG32 PLL : 1;
__REG32 : 2;
__REG32 MPU : 1;
__REG32 MAXADCSPD : 4;
__REG32 MINSYSDIV : 4;
__REG32 ADC : 1;
__REG32 : 3;
__REG32 PWM : 1;
__REG32 :11;
} __dc1_bits;
/* Device Capabilities 2 (DC2) */
typedef struct {
__REG32 UART0 : 1;
__REG32 UART1 : 1;
__REG32 : 2;
__REG32 SSI : 1;
__REG32 : 7;
__REG32 I2C : 1;
__REG32 : 3;
__REG32 GPTM0 : 1;
__REG32 GPTM1 : 1;
__REG32 GPTM2 : 1;
__REG32 : 5;
__REG32 COMP0 : 1;
__REG32 : 7;
} __dc2_bits;
/* Device Capabilities 3 (DC3) */
typedef struct {
__REG32 PWM0 : 1;
__REG32 PWM1 : 1;
__REG32 PWM2 : 1;
__REG32 PWM3 : 1;
__REG32 PWM4 : 1;
__REG32 PWM5 : 1;
__REG32 C0_N : 1;
__REG32 C0_P : 1;
__REG32 C0_O : 1;
__REG32 : 7;
__REG32 ADC0 : 1;
__REG32 ADC1 : 1;
__REG32 ADC2 : 1;
__REG32 ADC3 : 1;
__REG32 : 4;
__REG32 CCP0 : 1;
__REG32 CCP1 : 1;
__REG32 CCP2 : 1;
__REG32 CCP3 : 1;
__REG32 CCP4 : 1;
__REG32 CCP5 : 1;
__REG32 : 2;
} __dc3_bits;
/* Device Capabilities 4 (DC4) */
typedef struct {
__REG32 PORTA : 1;
__REG32 PORTB : 1;
__REG32 PORTC : 1;
__REG32 PORTD : 1;
__REG32 PORTE : 1;
__REG32 :27;
} __dc4_bits;
/* Power-On and Brown-Out Reset Control (PBORCTL) */
typedef struct {
__REG32 BORWT : 1;
__REG32 BORIOR : 1;
__REG32 BORTIM :14;
__REG32 :16;
} __pborctl_bits;
/* LDO Power Control (LDOPCTL) */
typedef struct {
__REG32 VADJ : 6;
__REG32 :26;
} __ldopctl_bits;
/* Software Reset Control 0 (SRCR0) */
typedef struct {
__REG32 : 3;
__REG32 WDT : 1;
__REG32 :12;
__REG32 ADC : 1;
__REG32 : 3;
__REG32 PWM : 1;
__REG32 :11;
} __srcr0_bits;
/* Software Reset Control 1 (SRCR1) */
typedef struct {
__REG32 UART0 : 1;
__REG32 UART1 : 1;
__REG32 : 2;
__REG32 SSI : 1;
__REG32 : 7;
__REG32 I2C : 1;
__REG32 : 3;
__REG32 GPTM0 : 1;
__REG32 GPTM1 : 1;
__REG32 GPTM2 : 1;
__REG32 :13;
} __srcr1_bits;
/* Software Reset Control 2 (SRCR2) */
typedef struct {
__REG32 PORTA : 1;
__REG32 PORTB : 1;
__REG32 PORTC : 1;
__REG32 PORTD : 1;
__REG32 PORTE : 1;
__REG32 :27;
} __srcr2_bits;
/* Raw Interrupt Status (RIS) */
typedef struct {
__REG32 PLLFRIS : 1;
__REG32 BORRIS : 1;
__REG32 LDORIS : 1;
__REG32 MOFRIS : 1;
__REG32 BOFRIS : 1;
__REG32 CLRIS : 1;
__REG32 PLLLRIS : 1;
__REG32 :25;
} __ris_bits;
/* Interrupt Mask Control (IMC) */
typedef struct {
__REG32 PLLFIM : 1;
__REG32 BORIM : 1;
__REG32 LDOIM : 1;
__REG32 MOFIM : 1;
__REG32 BOFIM : 1;
__REG32 CLIM : 1;
__REG32 PLLLIM : 1;
__REG32 :25;
} __imc_bits;
/* Masked Interrupt Status and Clear (MISC) */
typedef struct {
__REG32 PLLFMIS : 1;
__REG32 BORMIS : 1;
__REG32 LDOMIS : 1;
__REG32 MOFMIS : 1;
__REG32 BOFMIS : 1;
__REG32 CLMIS : 1;
__REG32 PLLLMIS : 1;
__REG32 :25;
} __misc_bits;
/* Reset Cause (RESC) */
typedef struct {
__REG32 EXT : 1;
__REG32 POR : 1;
__REG32 BOR : 1;
__REG32 WDT : 1;
__REG32 SW : 1;
__REG32 LDO : 1;
__REG32 :26;
} __resc_bits;
/* Run-Mode Clock Configuration (RCC) */
typedef struct {
__REG32 : 2;
__REG32 MOSCVER : 1;
__REG32 BOSCVER : 1;
__REG32 OSCSRC : 2;
__REG32 XTAL : 4;
__REG32 PLLVER : 1;
__REG32 BYPASS : 1;
__REG32 OEN : 1;
__REG32 PWRDN : 1;
__REG32 : 8;
__REG32 USESYS : 1;
__REG32 SYSDIV : 4;
__REG32 ACG : 1;
__REG32 : 4;
} __rcc_bits;
/* XTAL to PLL Translation (PLLCFG) */
typedef struct {
__REG32 R : 5;
__REG32 F : 9;
__REG32 OD : 2;
__REG32 :16;
} __pllcfg_bits;
/* Run-Mode Clock Gating Control 0 (RCGC0)
Sleep-Mode Clock Gating Control 0 (SCGC0)
Deep-Sleep-Mode Clock Gating Control 0 (DCGC0) */
typedef struct {
__REG32 JTAG : 1;
__REG32 SWD : 1;
__REG32 SWO : 1;
__REG32 WDT : 1;
__REG32 : 4;
__REG32 MAXADCSPD : 4;
__REG32 : 4;
__REG32 ADC : 1;
__REG32 : 3;
__REG32 PWM : 1;
__REG32 :11;
} __rcgc0_bits;
/* Run-Mode Clock Gating Control 1 (RCGC1)
Sleep-Mode Clock Gating Control 1 (SCGC1)
Deep-Sleep-Mode Clock Gating Control 1 (DCGC1) */
typedef struct {
__REG32 UART0 : 1;
__REG32 UART1 : 1;
__REG32 : 2;
__REG32 SSI : 1;
__REG32 : 7;
__REG32 I2C : 1;
__REG32 : 3;
__REG32 GPTM0 : 1;
__REG32 GPTM1 : 1;
__REG32 GPTM2 : 1;
__REG32 :13;
} __rcgc1_bits;
/* Run-Mode Clock Gating Control 2 (RCGC2)
Sleep-Mode Clock Gating Control 2 (SCGC2)
Deep-Sleep-Mode Clock Gating Control 2 (DCGC2) */
typedef struct {
__REG32 PORTA : 1;
__REG32 PORTB : 1;
__REG32 PORTC : 1;
__REG32 PORTD : 1;
__REG32 PORTE : 1;
__REG32 :27;
} __rcgc2_bits;
/* Clock Verification Clear (CLKVCLR) */
typedef struct {
__REG32 VERCLR : 1;
__REG32 :31;
} __clkvclr_bits;
/* Allow Unregulated LDO to Reset the Part (LDOARST) */
typedef struct {
__REG32 LDOARST : 1;
__REG32 :31;
} __ldoarst_bits;
/* Flash Memory Protection Read Enable (FMPRE)
Flash Memory Protection Program Enable (FMPPE) */
typedef struct {
__REG32 BLOCK0 : 1;
__REG32 BLOCK1 : 1;
__REG32 BLOCK2 : 1;
__REG32 BLOCK3 : 1;
__REG32 :28;
} __fmpre_bits;
/* Flash Memory Address (FMA) */
typedef struct {
__REG32 OFFSET :12;
__REG32 :20;
} __fma_bits;
/* Flash Memory Control (FMC) */
typedef struct {
__REG32 WRITE : 1;
__REG32 ERASE : 1;
__REG32 MERASE : 1;
__REG32 COMT : 1;
__REG32 :12;
__REG32 WRKEY :16;
} __fmc_bits;
/* Flash Controller Raw Interrupt Status (FCRIS) */
typedef struct {
__REG32 ARIS : 1;
__REG32 PRIS : 1;
__REG32 :30;
} __fcris_bits;
/* Flash Controller Interrupt Mask (FCIM) */
typedef struct {
__REG32 AMASK : 1;
__REG32 PMASK : 1;
__REG32 :30;
} __fcim_bits;
/* Flash Controller Masked Interrupt Status and Clear (FCMISC) */
typedef struct {
__REG32 AMISC : 1;
__REG32 PMISC : 1;
__REG32 :30;
} __fcmisc_bits;
/* GPIO registers */
typedef struct {
__REG32 no0 : 1;
__REG32 no1 : 1;
__REG32 no2 : 1;
__REG32 no3 : 1;
__REG32 no4 : 1;
__REG32 no5 : 1;
__REG32 no6 : 1;
__REG32 no7 : 1;
__REG32 :24;
} __gpio_bits;
/* GPTM Configuration (GPTMCFG) */
typedef struct {
__REG32 GPTMCFG : 3;
__REG32 :29;
} __gptmcfg_bits;
/* GPTM TimerA Mode (GPTMTAMR) */
typedef struct {
__REG32 TAMR : 2;
__REG32 TACMR : 1;
__REG32 TAAMS : 1;
__REG32 :28;
} __gptmtamr_bits;
/* GPTM TimerB Mode (GPTMTBMR) */
typedef struct {
__REG32 TBMR : 2;
__REG32 TBCMR : 1;
__REG32 TBAMS : 1;
__REG32 :28;
} __gptmtbmr_bits;
/* GPTM Control (GPTMCTL) */
typedef struct {
__REG32 TAEN : 1;
__REG32 TASTALL : 1;
__REG32 TAEVENT : 2;
__REG32 RTCEN : 1;
__REG32 TAOTE : 1;
__REG32 TAPWML : 1;
__REG32 : 1;
__REG32 TBEN : 1;
__REG32 TBSTALL : 1;
__REG32 TBEVENT : 2;
__REG32 : 1;
__REG32 TBOTE : 1;
__REG32 TBPWML : 1;
__REG32 :17;
} __gptmctl_bits;
/* GPTM Interrupt Mask (GPTMIMR) */
typedef struct {
__REG32 TATOIM : 1;
__REG32 C1MIM : 1;
__REG32 C1EIM : 1;
__REG32 RTCIM : 1;
__REG32 : 4;
__REG32 TBTOIM : 1;
__REG32 C2MIM : 1;
__REG32 C2EIM : 1;
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