iolpc2888_fields.h

基于 Philips 公司的 ARM-7 使用之 uC/OS-II 作业系统,此例程是移植于 LPC-2888 上的应用,不同于一般的 Porting 其最主要是加入了支援 OS_View 观察器功能

#define  MCICLEAR_CMDSENTCLR        0x00000080
#define  MCICLEAR_DATAENDCLR        0x00000100
#define  MCICLEAR_STARTBITERRCLR    0x00000200
#define  MCICLEAR_DATABLOCKENDCLR   0x00000400
#define  MCICLEAR_ALLCLR            0x000007FF

#define  MCIMASK_CMDCRCFAIL         0x00000001
#define  MCIMASK_DATACRCFAIL        0x00000002
#define  MCIMASK_CMDTIMEOUT         0x00000004
#define  MCIMASK_DATATIMEOUT        0x00000008
#define  MCIMASK_TXUNDERRUN         0x00000010
#define  MCIMASK_RXOVERRUN          0x00000020
#define  MCIMASK_CMDRESPEND         0x00000040
#define  MCIMASK_CMDSENT            0x00000080
#define  MCIMASK_DATAEND            0x00000100
#define  MCIMASK_STARTBITERR        0x00000200
#define  MCIMASK_DATABLOCKEND       0x00000400
#define  MCIMASK_CMDACTIVE          0x00000800
#define  MCIMASK_TXACTIVE           0x00001000
#define  MCIMASK_RXACTIVE           0x00002000
#define  MCIMASK_TXFIFOHALFEMPTY    0x00004000
#define  MCIMASK_RXFIFOHALFFULL     0x00008000
#define  MCIMASK_TXFIFOFULL         0x00010000
#define  MCIMASK_RXFIFOFULL         0x00020000
#define  MCIMASK_TXFIFOEMPTY        0x00040000
#define  MCIMASK_RXFIFOEMPTY        0x00080000
#define  MCIMASK_TXDATAAVLBL        0x00100000
#define  MCIMASK_RXDATAAVLBL        0x00200000
#define  MCIMASK_ALLMASK            0x003FFFFF;
#define  MCIMASK_NONEMASK           0x00000000;

#define  MCIMASK_DATATX            (MCIMASK_DATACRCFAIL         | MCIMASK_DATATIMEOUT       | \
                                    MCIMASK_TXUNDERRUN          | MCIMASK_STARTBITERR       | \
                                    MCIMASK_DATAEND             | MCIMASK_DATABLOCKEND      | \
                                    MCIMASK_TXACTIVE                                        )

#define  MCIMASK_DATARX            (MCIMASK_DATACRCFAIL         | MCIMASK_DATATIMEOUT       | \
                                    MCIMASK_RXOVERRUN           | MCIMASK_STARTBITERR       | \
                                    MCIMASK_DATAEND             | MCIMASK_DATABLOCKEND      | \
                                    MCIMASK_RXACTIVE                                        )

#define  MCIMASK_DATA              (MCIMASK_DATAEND             | MCISTATUS_DATABLOCKEND    | \
                                    MCIMASK_TXACTIVE            | MCIMASK_RXACTIVE          )

#define  MCIMASK_FIFO              (MCISTATUS_TXFIFOHALFEMPTY   | MCIMASK_RXFIFOHALFFULL    | \
                                    MCIMASK_TXFIFOFULL          | MCIMASK_RXFIFOFULL        | \
                                    MCIMASK_TXFIFOEMPTY         | MCIMASK_RXFIFOEMPTY       | \
                                    MCIMASK_TXDATAAVLBL         | MCIMASK_TXDATAAVLBL       )

#define  MCIMASK_ERROR             (MCIMASK_DATACRCFAIL         | MCIMASK_DATATIMEOUT       | \
                                    MCIMASK_TXUNDERRUN          | MCIMASK_RXOVERRUN         | \
                                    MCIMASK_STARTBITERR                                     )

#define  MCIMASK_CMD               (MCIMASK_CMDCRCFAIL          | MCIMASK_CMDTIMEOUT        | \
                                    MCIMASK_CMDRESPEND          | MCIMASK_CMDSENT           | \
                                    MCIMASK_CMDACTIVE                                       )

#define  MCIMASK_INTNOTERROR     ((~MCIMASK_ERROR) & 0x000007FF)

#define  MCISTATUS_ERROR            MCIMASK_ERROR

#define  MCISTATUS_INTNOTERROR      MCIMASK_NOTERROR

#define  MCICLKEN_MCICLKEN          0x00000001


/*
********************************************************************************************************
*                                              DMA IDs
********************************************************************************************************
*/

#define  DMA_ID_SDMMC_SINGLE                 1
#define  DMA_ID_SDMMC_BURST                  2
#define  DMA_ID_UART_RX                      3
#define  DMA_ID_UART_TX                      4
#define  DMA_ID_I2C                          5
#define  DMA_ID_SAO1_A                       6
#define  DMA_ID_SAO1_B                       7
#define  DMA_ID_SAO2_A                       8
#define  DMA_ID_SAO2_B                       9
#define  DMA_ID_SAI1_A                      10
#define  DMA_ID_SAI1_B                      11
#define  DMA_ID_SAI4_A                      12
#define  DMA_ID_SAI4_B                      13
#define  DMA_ID_LCD                         18
#define  DMA_ID_MPMC_A19                    19
#define  DMA_ID_MPMC_A17                    20


/*
********************************************************************************************************
*                                       DMA REGISTER VALUE DEFINES
********************************************************************************************************
*/

#define  DMALENGTH_LENGTH           0x00000FFF

#define  DMACONFIG_DESTID(x)        ((x) & 0x0000001F)
#define  DMACONFIG_DESTID_BUFFER    0x00000000
#define  DMACONFIG_SOURCEID(x)      (((x) << 5) & 0x000003E0)
#define  DMACONFIG_SOURCEID_BUFFER  0x00000000
#define  DMACONFIG_SIZE_32BITS      0x00000000
#define  DMACONFIG_SIZE_16BITS      0x00000400
#define  DMACONFIG_SIZE_8BITS       0x00000800
#define  DMACONFIG_SWAPENDIAN       0x00001000
#define  DMACONFIG_PAIREDCHANNEL    0x0000E000
#define  DMACONFIG_PAIREDCHAN_ENAB  0x00020000
#define  DMACONFIG_CIRCULARBUFFER   0x00040000

#define  DMAENAB_ENABLE             0x00000001
#define  DMAENAB_DISABLE            0x00000000

#define  DMACOUNT_COUNT             0x00000FFF

#define  DMA_ENABLE_CHANNEL0        0x00000001
#define  DMA_ENABLE_CHANNEL1        0x00000002
#define  DMA_ENABLE_CHANNEL2        0x00000004
#define  DMA_ENABLE_CHANNEL3        0x00000008
#define  DMA_ENABLE_CHANNEL4        0x00000010
#define  DMA_ENABLE_CHANNEL5        0x00000020
#define  DMA_ENABLE_CHANNEL6        0x00000040
#define  DMA_ENABLE_CHANNEL7        0x00000080

#define  DMA_STAT_COMPLETE0         0x00000001
#define  DMA_STAT_HALF0             0x00000002
#define  DMA_STAT_COMPLETE1         0x00000004
#define  DMA_STAT_HALF1             0x00000008
#define  DMA_STAT_COMPLETE2         0x00000010
#define  DMA_STAT_HALF2             0x00000020
#define  DMA_STAT_COMPLETE3         0x00000040
#define  DMA_STAT_HALF3             0x00000080
#define  DMA_STAT_COMPLETE4         0x00000100
#define  DMA_STAT_HALF4             0x00000200
#define  DMA_STAT_COMPLETE5         0x00000400
#define  DMA_STAT_HALF5             0x00000800
#define  DMA_STAT_COMPLETE6         0x00001000
#define  DMA_STAT_HALF6             0x00002000
#define  DMA_STAT_COMPLETE7         0x00004000
#define  DMA_STAT_HALF7             0x00008000
#define  DMA_STAT_SOFTINT           0x40000000
#define  DMA_STAT_ABORT             0x80000000
#define  DMA_STAT_ALL               0xC000FFFF

#define  DMA_IRQMASK_COMPLETE0      0x00000001
#define  DMA_IRQMASK_HALF0          0x00000002
#define  DMA_IRQMASK_COMPLETE1      0x00000004
#define  DMA_IRQMASK_HALF1          0x00000008
#define  DMA_IRQMASK_COMPLETE2      0x00000010
#define  DMA_IRQMASK_HALF2          0x00000020
#define  DMA_IRQMASK_COMPLETE3      0x00000040
#define  DMA_IRQMASK_HALF3          0x00000080
#define  DMA_IRQMASK_COMPLETE4      0x00000100
#define  DMA_IRQMASK_HALF4          0x00000200
#define  DMA_IRQMASK_COMPLETE5      0x00000400
#define  DMA_IRQMASK_HALF5          0x00000800
#define  DMA_IRQMASK_COMPLETE6      0x00001000
#define  DMA_IRQMASK_HALF6          0x00002000
#define  DMA_IRQMASK_COMPLETE7      0x00004000
#define  DMA_IRQMASK_HALF7          0x00008000
#define  DMA_IRQMASK_SOFTINT        0x40000000
#define  DMA_IRQMASK_ABORT          0x80000000
#define  DMA_IRQMASK_ALL            0xC000FFFF

#define  DMA3EXTEN_ENABLE           0x00000001
#define  DMA3EXTEN_DIAABLE          0x00000000

#define  DMA5EXTEN_ENABLE           0x00000001
#define  DMA5EXTEN_DISABLE          0x00000000




#endif