iolpc2888.h

基于 Philips 公司的 ARM-7 使用之 uC/OS-II 作业系统,此例程是移植于 LPC-2888 上的应用,不同于一般的 Porting 其最主要是加入了支援 OS_View 观察器功能

__REG32 LCDREAD   :1;
__REG32 LCDBUSY   :1;
__REG32 FIFOLEV   :5;
__REG32           :22;
} __lcdstat_bits;

/* LCD Raw Interrupt Status Register (LCDISTAT - 0x8010 0008) Read Only */
typedef struct{
__REG32 LCDFIFOMT :1;
__REG32 LCDFIFOH  :1;
__REG32           :1;
__REG32 LCDREAD   :1;
__REG32           :28;
} __lcdistat_bits;

/* LCD Interrupt Mask Register (LCDIMASK - 0x8010 3010) */
typedef struct{
__REG32 LCDFIFOMT :1;
__REG32 LCDFIFOH  :1;
__REG32 LCDOVER   :1;
__REG32 LCDREAD   :1;
__REG32           :28;
} __lcdimask_bits;

/* LCD Read Command Register (LCDREAD - 0x8010 3014) Write Only */
typedef struct{
__REG32 LCDDATA :1;
__REG32         :31;
} __lcdread_bits;

/* LCD Instruction Byte Register (LCDIBYTE - 0x8010 3020) */
typedef struct{
__REG32 IBYTE :8;
__REG32       :24;
} __lcdibyte_bits;

/* LCD Data Byte Register (LCDDBYTE - 0x8010 3030) */
typedef struct{
__REG32 DBYTE :8;
__REG32       :24;
} __lcddbyte_bits;

/* LCD Data Word Register (LCDDWORD - 0x8010 3080) Write Only */
typedef struct{
__REG32  DWORD :8;
__REG32        :24;
} __lcddword_bits;

/* Bit/Signal correspondence in Port 0 (EMC) registers */
typedef struct{
  __REG32 P0_0   :1;
  __REG32 P0_1   :1;
  __REG32 P0_2   :1;
  __REG32 P0_3   :1;
  __REG32 P0_4   :1;
  __REG32 P0_5   :1;
  __REG32 P0_6   :1;
  __REG32 P0_7   :1;
  __REG32 P0_8   :1;
  __REG32 P0_9   :1;
  __REG32 P0_10  :1;
  __REG32 P0_11  :1;
  __REG32 P0_12  :1;
  __REG32 P0_13  :1;
  __REG32 P0_14  :1;
  __REG32 P0_15  :1;
  __REG32 P0_16  :1;
  __REG32 P0_17  :1;
  __REG32 P0_18  :1;
  __REG32 P0_19  :1;
  __REG32 P0_20  :1;
  __REG32 P0_21  :1;
  __REG32 P0_22  :1;
  __REG32 P0_23  :1;
  __REG32 P0_24  :1;
  __REG32 P0_25  :1;
  __REG32 P0_26  :1;
  __REG32 P0_27  :1;
  __REG32 P0_28  :1;
  __REG32 P0_29  :1;
  __REG32 P0_30  :1;
  __REG32 P0_31  :1;
} __port0_bits;

/* Bit/Signal correspondence in input group 1 (EMC) registers */
typedef struct{
    __REG32 A16   :1;
    __REG32 A17   :1;
    __REG32 A18   :1;
    __REG32 A19   :1;
    __REG32 A20   :1;
    __REG32 STCS0 :1;
    __REG32 STCS1 :1;
    __REG32 STCS2 :1;
    __REG32 DYCS  :1;
    __REG32 CKE   :1;
    __REG32 DQM0  :1;
    __REG32 DQM1  :1;
    __REG32 BLS0  :1;
    __REG32 BLS1  :1;
    __REG32 MCLKO :1;
    __REG32 WE    :1;
    __REG32 CAS   :1;
    __REG32 RAS   :1;
    __REG32 OE    :1;
    __REG32 PRO   :1;
    __REG32       :12;
} __port1_bits;

/* Bit/Signal correspondence in Port 2 (GPIO) registers */
typedef struct {
    __REG32 P2_0 :1;
    __REG32 P2_1 :1;
    __REG32 P2_2 :1;
    __REG32 P2_3 :1;
    __REG32      :28;
} __port2_bits;

/* Bit/Signal correspondence in Port 3 (DAI/DAO) registers */
typedef struct{
__REG32 P3_0 :1;
__REG32 P3_1 :1;
__REG32 P3_2 :1;
__REG32 P3_3 :1;
__REG32      :1;
__REG32 P3_5 :1;
__REG32 P3_6 :1;
__REG32      :25;
} __port3_bits;

/* Bit/Signal correspondence in Port 4 (LCD) registers */
typedef struct{
__REG32 P4_0  :1;
__REG32 P4_1  :1;
__REG32 P4_2  :1;
__REG32 P4_3  :1;
__REG32 P4_4  :1;
__REG32 P4_5  :1;
__REG32 P4_6  :1;
__REG32 P4_7  :1;
__REG32 P4_8  :1;
__REG32 P4_9  :1;
__REG32 P4_10 :1;
__REG32 P4_11 :1;
__REG32       :20;
} __port4_bits;

/* Bit/Signal correspondence in Port 5 (MCI/SD) registers */
typedef struct{
__REG32 P5_0 :1;
__REG32 P5_1 :1;
__REG32 P5_2 :1;
__REG32 P5_3 :1;
__REG32 P5_4 :1;
__REG32 P5_5 :1;
__REG32      :26;
} __port5_bits;

/* Bit/Signal correspondence in Port 6 (UART) registers */
typedef struct{
__REG32 P6_0 :1;
__REG32 P6_1 :1;
__REG32 P6_2 :1;
__REG32 P6_3 :1;
__REG32      :28;
} __port6_bits;

/* Port 7 (USB) Registers */
typedef struct{
__REG32 P7_0 :1;
__REG32      :31;
} __port7_bits;

/* Bit/Signal correspondence in input group 0 registers */
typedef struct{
__REG32 START  :1;
__REG32 ATARDY :1;
__REG32 P0_0   :1;
__REG32 P0_1   :1;
__REG32 P0_2   :1;
__REG32 P0_3   :1;
__REG32 P0_4   :1;
__REG32 P0_5   :1;
__REG32 P0_6   :1;
__REG32 P0_7   :1;
__REG32 P0_8   :1;
__REG32 P0_9   :1;
__REG32 P0_10  :1;
__REG32 P0_11  :1;
__REG32 P0_12  :1;
__REG32 P0_13  :1;
__REG32 P0_14  :1;
__REG32 P0_15  :1;
__REG32 P0_16  :1;
__REG32 P0_17  :1;
__REG32 P0_18  :1;
__REG32 P0_19  :1;
__REG32 P0_20  :1;
__REG32 P0_21  :1;
__REG32 P0_22  :1;
__REG32 P0_23  :1;
__REG32 P0_24  :1;
__REG32 P0_25  :1;
__REG32 P0_26  :1;
__REG32 P0_27  :1;
__REG32 P0_28  :1;
__REG32 P0_29  :1;
} __igroup0_bits;

/* Bit/Signal correspondence in input group 1 registers */
typedef struct{
__REG32 P0_30 :1;
__REG32 P0_31 :1;
__REG32 P1_0  :1;
__REG32 P1_1  :1;
__REG32 P1_2  :1;
__REG32 P1_3  :1;
__REG32 P1_4  :1;
__REG32 P1_5  :1;
__REG32 P1_6  :1;
__REG32 P1_7  :1;
__REG32 P1_8  :1;
__REG32 P1_9  :1;
__REG32 P1_10 :1;
__REG32 P1_11 :1;
__REG32 P1_12 :1;
__REG32 P1_13 :1;
__REG32 P1_14 :1;
__REG32 P1_15 :1;
__REG32 P1_16 :1;
__REG32 P1_17 :1;
__REG32 P1_18 :1;
__REG32 P1_19 :1;
__REG32 P3_0  :1;
__REG32 P3_1  :1;
__REG32 P3_2  :1;
__REG32 WSO   :1;
__REG32 P3_5  :1;
__REG32 P3_6  :1;
__REG32 P4_0  :1;
__REG32 P4_1  :1;
__REG32 P4_2  :1;
__REG32 P4_3  :1;
} __igroup1_bits;

/* Bit/Signal correspondence in input group 2 registers */
typedef struct{
__REG32 P4_4      :1;
__REG32 P4_5      :1;
__REG32 P4_6      :1;
__REG32 P4_7      :1;
__REG32 P4_8      :1;
__REG32 P4_9      :1;
__REG32 P4_10     :1;
__REG32 P4_11     :1;
__REG32 P3_3      :1;
__REG32 P5_0      :1;
__REG32 P5_1      :1;
__REG32 P5_2      :1;
__REG32 P5_3      :1;
__REG32 P5_4      :1;
__REG32 P5_5      :1;
__REG32 P6_0      :1;
__REG32 P6_1      :1;
__REG32 P6_2      :1;
__REG32 P6_3      :1;
__REG32 CACHEFIQ  :1;
__REG32 CACHEIRQ  :1;
__REG32 T0CT1     :1;
__REG32 T1CT1     :1;
__REG32 RTCINT    :1;
__REG32 ADCINT    :1;
__REG32 P5_5_1    :1;
__REG32 P5_4_1    :1;
__REG32 P5_3_1    :1;
__REG32 P5_2_1    :1;
__REG32 WDOG      :1;
__REG32 P6_0_1    :1;
__REG32 SCL       :1;
} __igroup2_bits;

/* Bit/Signal correspondence in input group 3 registers */
typedef struct{
__REG32             :2;
__REG32 P2_0        :1;
__REG32 P2_1        :1;
__REG32 P2_2        :1;
__REG32 P2_3        :1;
__REG32 USBGOSUSP   :1;
__REG32 USBWKUPPCS  :1;
__REG32 USBPWROFF   :1;
__REG32 P7_0        :1;
__REG32 USBBUSRES   :1;
__REG32             :21;
} __igroup3_bits;

/* Event Router Output Register (EVOUT - 0x8000 0D40) */
typedef struct{
__REG32 INT0   :1;
__REG32 INT1   :1;
__REG32 INT2   :1;
__REG32 INT3   :1;
__REG32 WAKEUP :1;
__REG32        :27;
} __evout_bits;

/* Features Register (EVFEATURES - 0x8000 0E00) */
typedef struct{
__REG32 N :8;
__REG32   :8;
__REG32 M :6;
__REG32   :10;
} __evfeatures_bits;

#endif    /* __IAR_SYSTEMS_ICC__ */

/* Common declarations  ****************************************************/
/***************************************************************************
 **
 ** System control
 **
 ***************************************************************************/
__IO_REG32_BIT(SYS_BOOTMAP,     0x80005070,__READ_WRITE,__sys_bootmap_bits);
__IO_REG32_BIT(SYS_BOOTADDR,    0x80005074,__READ_WRITE,__sys_bootaddr_bits);
__IO_REG32    (SYS_PARTID,      0x8000507C,__READ      );

/***************************************************************************
 **
 ** Cache and memory mapping
 **
 ***************************************************************************/
__IO_REG32_BIT(CACHE_RST_STAT ,0x80104000,__READ      ,__cache_rst_stat_bits);
__IO_REG32_BIT(CACHE_SETTINGS ,0x80104004,__READ_WRITE,__cache_settings_bits);
__IO_REG32_BIT(CACHE_PAGE_CTRL,0x80104008,__READ_WRITE,__cache_page_ctrl_bits);
__IO_REG32(    C_RD_MISSES    ,0x8010400C,__READ      );
__IO_REG32(    C_FLUSHES      ,0x80104010,__READ      );
__IO_REG32(    C_WR_MISSES    ,0x80104014,__READ      );
__IO_REG32_BIT(ADDRESS_PAGE_0 ,0x80104018,__READ_WRITE,__address_page_n_bits);
__IO_REG32_BIT(ADDRESS_PAGE_1 ,0x8010401C,__READ_WRITE,__address_page_n_bits);
__IO_REG32_BIT(ADDRESS_PAGE_2 ,0x80104020,__READ_WRITE,__address_page_n_bits);
__IO_REG32_BIT(ADDRESS_PAGE_3 ,0x80104024,__READ_WRITE,__address_page_n_bits);
__IO_REG32_BIT(ADDRESS_PAGE_4 ,0x80104028,__READ_WRITE,__address_page_n_bits);
__IO_REG32_BIT(ADDRESS_PAGE_5 ,0x8010402C,__READ_WRITE,__address_page_n_bits);
__IO_REG32_BIT(ADDRESS_PAGE_6 ,0x80104030,__READ_WRITE,__address_page_n_bits);
__IO_REG32_BIT(ADDRESS_PAGE_7 ,0x80104034,__READ_WRITE,__address_page_n_bits);
__IO_REG32_BIT(ADDRESS_PAGE_8 ,0x80104038,__READ_WRITE,__address_page_n_bits);
__IO_REG32_BIT(ADDRESS_PAGE_9 ,0x8010403C,__READ_WRITE,__address_page_n_bits);
__IO_REG32_BIT(ADDRESS_PAGE_10,0x80104040,__READ_WRITE,__address_page_n_bits);
__IO_REG32_BIT(ADDRESS_PAGE_11,0x80104044,__READ_WRITE,__address_page_n_bits);
__IO_REG32_BIT(ADDRESS_PAGE_12,0x80104048,__READ_WRITE,__address_page_n_bits);
__IO_REG32_BIT(ADDRESS_PAGE_13,0x8010404C,__READ_WRITE,__address_page_n_bits);
__IO_REG32_BIT(ADDRESS_PAGE_14,0x80104050,__READ_WRITE,__address_page_n_bits);
__IO_REG32_BIT(ADDRESS_PAGE_15,0x80104054,__READ_WRITE,__address_page_n_bits);
__IO_REG32_BIT(CPU_CLK_GATE   ,0x80104058,__READ_WRITE,__cpu_clk_gate_bits);

/***************************************************************************
 **
 ** Flash memory controller
 **
 ***************************************************************************/
__IO_REG32_BIT(F_CTRL,     0x80102000,__READ_WRITE,__f_ctrl_bits);
__IO_REG32_BIT(F_STAT,     0x80102004,__READ      ,__f_stat_bits);
__IO_REG32_BIT(F_PROG_TIME,0x80102008,__READ_WRITE,__f_prog_time_bits);
__IO_REG32_BIT(F_WAIT,     0x80102010,__READ_WRITE,__f_wait_bits);
__IO_REG32_BIT(F_CLK_TIME, 0x8010201C,__READ_WRITE,__f_clk_time_bits);
__IO_REG32_BIT(F_INTEN_CLR,0x80102FD8,__WRITE     ,__f_inten_clr_bits);
__IO_REG32_BIT(F_INTEN_SET,0x80102FDC,__WRITE     ,__f_inten_set_bits);
__IO_REG32_BIT(F_INT_STAT, 0x80102FE0,__READ      ,__f_int_stat_bits);
__IO_REG32_BIT(F_INTEN,    0x80102FE4,__READ      ,__f_inten_bits);
__IO_REG32_BIT(F_INT_CLR,  0x80102FE8,__WRITE     ,__f_int_clr_bits);
__IO_REG32_BIT(F_INT_SET,  0x80102FEC,__WRITE     ,__f_int_set_bits);
__IO_REG32_BIT(FLASH_PD,   0x80005030,__READ_WRITE,__flash_pd_bits);
__IO_REG32_BIT(FLASH_INIT, 0x80005034,__READ_WRITE,__flash_init_bits);

/***************************************************************************
 **
 ** DC-DC
 **
 ***************************************************************************/
__IO_REG32_BIT(DCDCADJUST1,0x80005004,__READ_WRITE,__dcdcadjust1_bits);
__IO_REG32_BIT(DCDCADJUST2,0x80005008,__READ_WRITE,__dcdcadjust2_bits);
__IO_REG32_BIT(DCDCCLKSEL, 0x8000500C,__READ_WRITE,__dcdcclksel_bits);

/***************************************************************************
 **
 ** Clock generation unit
 **
 ***************************************************************************/
__IO_REG32_BIT(PMODE,  0x80004C00,__READ_WRITE,__pmode_bits);
__IO_REG32_BIT(WDBARK, 0x80004C04,__READ      ,__wdbark_bits);
__IO_REG32_BIT(OSC32EN,0x80004C08,__READ_WRITE,__osc32en_bits);
__IO_REG32_BIT(OSCEN,  0x80004C10,__READ_WRITE,__oscen_bits);

/***************************************************************************
 **
 ** Main PLL
 **
 ***************************************************************************/
__IO_REG32(LPFIN,   0x80004CE4,__READ_WRITE);  /* changed */
__IO_REG32(LPPDN,   0x80004CE8,__READ_WRITE);  /* changed */
__IO_REG32(LPMBYP,  0x80004CEC,__READ_WRITE);  /* changed */
__IO_REG32(LPLOCK,  0x80004CF0,__READ      );  /* changed */
__IO_REG32(LPDBYP,  0x80004CF4,__READ_WRITE);  /* changed */
__IO_REG32(LPMSEL,  0x80004CF8,__READ_WRITE);  /* changed */
__IO_REG32(LPPSEL,  0x80004CFC,__READ_WRITE);  /* changed */

/***************************************************************************
 **
 ** High speed PLL
 **
 ***************************************************************************/
__IO_REG32_BIT(HPFIN, 0x800000AC,__READ_WRITE,__hpfin_bits);
__IO_REG32_BIT(HPNDEC,0x800000B4,__READ_WRITE,__hpndec_bits);
__IO_REG32_BIT(HPMDEC,0x800000B0,__READ_WRITE,__hpmdec_bits);
__IO_REG32_BIT(HPPDEC,0x800000B8,__READ_WRITE,__hppdec_bits);
__IO_REG32_BIT(HPMODE,0x800000BC,__READ_WRITE,__hpmode_bits);
__IO_REG32_BIT(HPSTAT,0x800000C0,__READ      ,__hpstat_bits);
__IO_REG32_BIT(HPREQ, 0x800000C8,__READ_WRITE,__hpreq_bits);
__IO_REG32_BIT(HPACK, 0x800000C4,__READ      ,__hpack_bits);
__IO_REG32_BIT(HPSELR,0x800000D8,__READ_WRITE,__hpselr_bits);
__IO_REG32_BIT(HPSELI,0x800000DC,__READ_WRITE,__hpseli_bits);
__IO_REG32_BIT(HPSELP,0x800000E0,__READ_WRITE,__hpselp_bits);

/***************************************************************************
 **
 ** Selection stage
 **
 ***************************************************************************/
__IO_REG32_BIT(SYSSCR,  0x80004000,__READ_WRITE,__sysscr_daiscr_bits);
__IO_REG32_BIT(APB0SCR, 0x80004004,__READ_WRITE,__sysscr_daiscr_bits);
__IO_REG32_BIT(APB1SCR, 0x80004008,__READ_WRITE,__sysscr_daiscr_bits);
__IO_REG32_BIT(APB3SCR, 0x8000400C,__READ_WRITE,__sysscr_daiscr_bits);
__IO_REG32_BIT(DCDCSCR, 0x80004010,__READ_WRITE,__sysscr_daiscr_bits);
__IO_REG32_BIT(RTCSCR,  0x80004014,__READ_WRITE,__sysscr_daiscr_bits);
__IO_REG32_BIT(MCISCR,  0x80004018,__READ_WRITE,__sysscr_daiscr_bits);
__IO_REG32_BIT(UARTSCR, 0x8000401C,__READ_WRITE,__sysscr_daiscr_bits);
__IO_REG32_BIT(DAIOSCR, 0x80004020,__READ_WRITE,__sysscr_daiscr_bits);
__IO_REG32_BIT(DAISCR,  0x80004024,__READ_WRITE,__sysscr_daiscr_bits);

__IO_REG32_BIT(SYSFSR1, 0x8000402C,__READ_WRITE,__sysfsr1_daifsr1_bits);
__IO_REG32_BIT(APB0FSR1,0x80004030,__READ_WRITE,__sysfsr1_daifsr1_bits);
__IO_REG32_BIT(APB1FSR1,0x80004034,__READ_WRITE,__sysfsr1_daifsr1_bits);
__IO_REG32_BIT(APB3FSR1,0x80004038,__READ_WRITE,__sysfsr1_daifsr1_bits);
__IO_REG32_BIT(DCDCFSR1,0x8000403C,__READ_WRITE,__sysfsr1_daifsr1_bits);
__IO_REG32_BIT(RTCFSR1, 0x80004040,__READ_WRITE,__sysfsr1_daifsr1_bits);
__IO_REG32_BIT(MCIFSR1, 0x80004044,__READ_WRITE,__sysfsr1_daifsr1_bits);
__IO_REG32_BIT(UARTFSR1,0x80004048,__READ_WRITE,__sysfsr1_daifsr1_bits);
__IO_REG32_BIT(DAIOFSR1,0x8000404C,__READ_WRITE,__sysfsr1_daifsr1_bits);
__IO_REG32_BIT(DAISFSR1,0x80004050,__READ_WRITE,__sysfsr1_daifsr1_bits);

__IO_REG32_BIT(SYSFSR2, 0x80004058,__READ_WRITE,__sysfsr1_daifsr1_bits);
__IO_REG32_BIT(APB0FSR2,0x8000405C,__READ_WRITE,__sysfsr1_daifsr1_bits);
__IO_REG32_BIT(APB1FSR2,0x80004060,__READ_WRITE,__sysfsr1_daifsr1_bits);
__IO_REG32_BIT(APB3FSR2,0x80004064,__READ_WRITE,__sysfsr1_daifsr1_bits);
__IO_REG32_BIT(DCDCFSR2,0x80004068,__READ_WRITE,__sysfsr1_daifsr1_bits);
__IO_REG32_BIT(RTCFSR2, 0x8000406C,__READ_WRITE,__sysfsr1_daifsr1_bits);
__IO_REG32_BIT(MCIFSR2, 0x80004070,__READ_WRITE,__sysfsr1_daifsr1_bits);
__IO_REG32_BIT(UARTFSR2,0x80004074,__READ_WRITE,__sysfsr1_daifsr1_bits);
__IO_REG32_BIT(DAIOFSR2,0x80004078,__READ_WRITE,__sysfsr1_daifsr1_bits);
__IO_REG32_BIT(DAISFSR2,0x8000407C,__READ_WRITE,__sysfsr1_daifsr1_bits);

__IO_REG32_BIT(SYSSSR,  0x80004084,__READ,__sysssr_daissr_bits);
__IO_REG32_BIT(APB0SSR, 0x80004088,__READ,__sysssr_daissr_bits);
__IO_REG32_BIT(APB1SSR, 0x8000408C,__READ,__sysssr_daissr_bits);
__IO_REG32_BIT(APB3SSR, 0x80004090,__READ,__sysssr_daissr_bits);
__IO_REG32_BIT(DCDCSSR, 0x80004094,__READ,__sysssr_daissr_bits);
__IO_REG32_BIT(RTCSSR,  0x80004098,__READ,__sysssr_daissr_bits);
__IO_REG32_BIT(MCISSR,  0x8000409C,__READ,__sysssr_daissr_bits);
__IO_REG32_BIT(UARTSSR, 0x800040A0,__READ,__sysssr_daissr_bits);
__IO_REG32_BIT(DAIOSSR, 0x800040A4,__READ,__sysssr_daissr_bits);
__IO_REG32_BIT(DAISSR,  0x800040A8,__READ,__sysssr_daissr_bits);

__IO_REG32_BIT(SYSBCR,  0x800043F0,__READ_WRITE,__sysbcr_daiobcr_bits);
__IO_REG32_BIT(APB0BCR, 0x800043F4,__READ_WRITE,__sysbcr_daiobcr_bits);
__IO_REG32_BIT(DAIOBCR, 0x800043F8,__READ_WRITE,__sysbcr_daiobcr_bits);

/***************************************************************************
 **
 ** Fractional divider
 **
 ***************************************************************************/
__IO_REG32_BIT(SYSFDCR0, 0x800043FC,__READ_WRITE,__sysfdcr_bits);
__IO_REG32_BIT(SYSFDCR1, 0x80004400,__READ_WRITE,__sysfdcr_bits);
__IO_REG32_BIT(SYSFDCR2, 0x80004404,__READ_WRITE,__sysfdcr_bits);
__IO_REG32_BIT(SYSFDCR3, 0x80004408,__READ_WRITE,__sysfdcr_bits);
__IO_REG32_BIT(SYSFDCR4, 0x8000440C,__READ_WRITE,__sysfdcr_bits);
__IO_REG32_BIT(SYSFDCR5, 0x80004410,__READ_WRITE,__sysfdcr_bits);
__IO_REG32_BIT(APB0FDCR0,0x80004414,__READ_WRITE,__sysfdcr_bits);
__IO_REG32_BIT(APB0FDCR1,0x80004418,__READ_WRITE,__sysfdcr_bits);
__IO_REG32_BIT(APB1FDCR, 0x8000441C,__READ_WRITE,__sysfdcr_bits);
__IO_REG32_BIT(APB3FDCR, 0x80004420,__READ_WRITE,__sysfdcr_bits);
__IO_REG32_BIT(UARTFDCR, 0x80004424,__READ_WRITE,__sysfdcr_bits);
__IO_REG32_BIT(DAIOFDCR0,0x80004428,__READ_WRITE,__sysfdcr_bits);
__IO_REG32_BIT(DAIOFDCR1,0x8000442C,__READ_WRITE,__sysfdcr_bits);
__IO_REG32_BIT(DAIOFDCR2,0x80004430,__READ_WRITE,__sysfdcr_bits);
__IO_REG32_BIT(DAIOFDCR3,0x80004434,__READ_WRITE,__sysfdcr_bits);
__IO_REG32_BIT(DAIOFDCR4,0x80004438,__READ_WRITE,__daiofdcr4_bits);
__IO_REG32_BIT(DAIOFDCR5,0x8000443C,__READ_WRITE,__sysfdcr_bits);

/***************************************************************************
 **
 ** Power control
 **
 ***************************************************************************/
__IO_REG32_BIT(APB0PCR0,0x800040B0,__READ_WRITE,__power_control_bits);
__IO_REG32_BIT(APB3PCR0,0x800040BC,__READ_WRITE,__power_