iolpc2888.h

基于 Philips 公司的 ARM-7 使用之 uC/OS-II 作业系统,此例程是移植于 LPC-2888 上的应用,不同于一般的 Porting 其最主要是加入了支援 OS_View 观察器功能

__REG32       :16;
} __usbeintstat_bits;

/* USB Endpoint Interrupt Clear Register (USBEIntClr - 0x8004 10A0) */
typedef struct{
__REG32 CLR0RX :1;
__REG32 CLR0TX :1;
__REG32 CLR1RX :1;
__REG32 CLR1TX :1;
__REG32 CLR2RX :1;
__REG32 CLR2TX :1;
__REG32 CLR3RX :1;
__REG32 CLR3TX :1;
__REG32 CLR4RX :1;
__REG32 CLR4TX :1;
__REG32 CLR5RX :1;
__REG32 CLR5TX :1;
__REG32 CLR6RX :1;
__REG32 CLR6TX :1;
__REG32 CLR7RX :1;
__REG32 CLR7TX :1;
__REG32        :16;
} __usbeintclr_bits;

/* USB Endpoint Interrupt Set Register (USBEIntSet - 0x8004 10A4) */
typedef struct{
__REG32 SET0RX :1;
__REG32 SET0TX :1;
__REG32 SET1RX :1;
__REG32 SET1TX :1;
__REG32 SET2RX :1;
__REG32 SET2TX :1;
__REG32 SET3RX :1;
__REG32 SET3TX :1;
__REG32 SET4RX :1;
__REG32 SET4TX :1;
__REG32 SET5RX :1;
__REG32 SET5TX :1;
__REG32 SET6RX :1;
__REG32 SET6TX :1;
__REG32 SET7RX :1;
__REG32 SET7TX :1;
__REG32        :16;
} __usbeintset_bits;

/* USB Endpoint Interrupt Priority Register (USBEIntP - 0x8004 10A8) */
typedef struct{
__REG32 P0RX :1;
__REG32 P0TX :1;
__REG32 P1RX :1;
__REG32 P1TX :1;
__REG32 P2RX :1;
__REG32 P2TX :1;
__REG32 P3RX :1;
__REG32 P3TX :1;
__REG32 P4RX :1;
__REG32 P4TX :1;
__REG32 P5RX :1;
__REG32 P5TX :1;
__REG32 P6RX :1;
__REG32 P6TX :1;
__REG32 P7RX :1;
__REG32 P7TX :1;
__REG32      :16;
} __usbeintp_bits;

/* USB Test Mode Register (USBTMode - 0x8004 1084) */
typedef struct{
__REG32 SE0NAK  :1;
__REG32 JSTATE  :1;
__REG32 KSTATE  :1;
__REG32 PRBS    :1;
__REG32 FORCEFS :1;
__REG32         :2;
__REG32 FORCEHS :1;
__REG32         :24;
} __usbtest_bits;

/* USB Clock Enable Register (USBClkEn - 0x8000 5050) */
typedef struct{
__REG32 CLKEN :1;
__REG32       :31;
} __usbclken_bits;

/* USB DMA Control Register (UDMACtrl - 0x8004 0400) */
typedef struct{
__REG32 UDMA_EN :1;
__REG32         :31;
} __udmactrl_bits;

/* USB DMA Software Reset Register (UDMASoftRes - 0x8004 0404) */
typedef struct{
__REG32 RSTCH0 :1;
__REG32 RSTCH1 :1;
__REG32        :30;
} __udmasoftres_bits;

/* USB DMA Status Register (UDMAStat - 0x8004 0408) */
typedef struct{
__REG32 CH0STAT :3;
__REG32         :1;
__REG32 CH1STAT :3;
__REG32         :25;
} __udmastat_bits;

/* USB DMA Channel Status Registers (UDMA0Stat - 0x8004 0000,
UDMA1Stat - 0x8004 0040) */
typedef struct{
__REG32 STATE :2;
__REG32       :14;
__REG32 WE    :1;
__REG32 DFCE  :1;
__REG32       :2;
__REG32 RE    :1;
__REG32 SFCE  :1;
__REG32 UE    :1;
__REG32 CE    :1;
__REG32       :8;
} __udma0stat_bits;

/* USB DMA Interrupt Status Register (UDMAIntStat - 0x8004 0410) */
typedef struct{
__REG32           :1;
__REG32 CH0IEOT   :1;
__REG32 CH0IERROR :1;
__REG32           :2;
__REG32 CH1IEOT   :1;
__REG32 CH1IERROR :1;
__REG32           :25;
} __udmaintstat_bits;

/* USB DMA Interrupt Enable Register (UDMAIntEn - 0x8004 0418) */
typedef struct{
__REG32             :1;
__REG32 CH0IEOTEN   :1;
__REG32 CH0IERROREN :1;
__REG32             :2;
__REG32 CH1IEOTEN   :1;
__REG32 CH1IERROREN :1;
__REG32             :25;
} __udmainten_bits;

/* USB DMA Interrupt Disable Register (UDMAIntDis - 0x8004 0420) */
typedef struct{
__REG32               :1;
__REG32 CH0IEOTDIS    :1;
__REG32 CH0IERRORDIS  :1;
__REG32               :2;
__REG32 CH1IEOTDIS    :1;
__REG32 CH1IERRORDIS  :1;
__REG32               :25;
} __udmaintdis_bits;

/* USB DMA Interrupt Clear Register (UDMAIntClr - 0x8004 0430) */
typedef struct{
__REG32               :1;
__REG32 CH0IEOTCLR    :1;
__REG32 CH0IERRORCLR  :1;
__REG32               :2;
__REG32 CH1IEOTCLR    :1;
__REG32 CH1IERRORCLR  :1;
__REG32               :25;
} __udmaintclr_bits;

/* USB DMA Interrupt Set Register (UDMAIntSet - 0x8004 0428) */
typedef struct{
__REG32               :1;
__REG32 CH0IEOTSET    :1;
__REG32 CH0IERRORSET  :1;
__REG32               :2;
__REG32 CH1IEOTSET    :1;
__REG32 CH1IERRORSET  :1;
__REG32               :25;
} __udmaintset_bits;

/* USB DMA Channel Control Registers (UDMA0Ctrl - 0x8004 0004 and
UDMA1Ctrl - 0x8004 0044) */
typedef struct{
__REG32 CHEN      :2;
__REG32           :1;
__REG32 SOURCE    :2;
__REG32 STYPE     :2;
__REG32 SA_ADJ    :2;
__REG32 SFC_MODE  :2;
__REG32 SFC_PORT  :4;
__REG32 DEST      :2;
__REG32 DTYPE     :2;
__REG32 DA_ADJ    :2;
__REG32 DFC_MODE  :2;
__REG32 DFC_PORT  :4;
__REG32           :3;
__REG32 IEOT_EN   :1;
__REG32 IERROR_EN :1;
} __udma0ctrl_bits;

/* USB DMA Channel Count Registers (UDMA0Throtl - 0x8004 0010 and
UDMA1Throtl - 0x8004 0050 */
typedef struct{
__REG32 STHROTTLE :16;
__REG32 DTHROTTLE :16;
} __udma0throtl_bits;

/* Stream I/O Configuration Register (SIOCR - 0x8020 0384) */
typedef struct{
__REG32        :7;
__REG32 DAI_OE :1;
__REG32        :24;
} __siocr_bits;

/* I2S Format Register (I2S_FMT - 0x8020 0380) */
typedef struct{
__REG32 DAI_FMT :3;
__REG32         :3;
__REG32 DAO_FMT :3;
__REG32         :23;
} __i2s_fmt_bits;

/* SAI1 Status Register (SAISTAT1 - 0x8020 0010) */
typedef struct{
__REG32 RUNDER  :1;
__REG32 LUNDER  :1;
__REG32 ROVER   :1;
__REG32 LOVER   :1;
__REG32 LFULL   :1;
__REG32 LHALF   :1;
__REG32 LNOTMT  :1;
__REG32 RFULL   :1;
__REG32 RHALF   :1;
__REG32 RNOTMT  :1;
__REG32         :22;
} __saistat1_bits;

/* SAI1 Mask Register (SAIMASK1 - 0x8020 0014) */
typedef struct{
__REG32 RUNMK   :1;
__REG32 LUNMK   :1;
__REG32 ROVMK   :1;
__REG32 LOVMK   :1;
__REG32 LFULMK  :1;
__REG32 LHALFMK :1;
__REG32 LNMTMK  :1;
__REG32 RFULMK  :1;
__REG32 RHALFMK :1;
__REG32 RNMTMK  :1;
__REG32         :22;
} __saimask1_bits;

/* SAO1 Status Register (SAOSTAT1 - 0x8020 0210) */
typedef struct{
__REG32 RUNDER :1;
__REG32 LUNDER :1;
__REG32 ROVER  :1;
__REG32 LOVER  :1;
__REG32 LFULL  :1;
__REG32 LHALF  :1;
__REG32 LMT    :1;
__REG32 RFULL  :1;
__REG32 RHALF  :1;
__REG32 RMT    :1;
__REG32        :22;
} __saostat1_bits;

/* SAO1 Mask Register (SAOMASK1 - 0x8020 0214) */
typedef struct{
__REG32 RUNMK   :1;
__REG32 LUNMK   :1;
__REG32 ROVMK   :1;
__REG32 LOVMK   :1;
__REG32 LFULLMK :1;
__REG32 LHALFMK :1;
__REG32 LMTMK   :1;
__REG32 RFULLMK :1;
__REG32 RHALFMK :1;
__REG32 RMTMK   :1;
__REG32         :22;
} __saomask1_bits;

/* Dual Analog In Control Register (DAINCTRL - 0x8020 03A4) */
typedef struct{
__REG32 RSD_PD    :1;
__REG32 LSD_PD    :1;
__REG32           :1;
__REG32 RPGA_GAIN :4;
__REG32 RPGA_PD   :1;
__REG32 LPGA_GAIN :4;
__REG32 LPGA_PD   :1;
__REG32           :19;
} __dainctrl_bits;

/* Dual ADC Control Register (DADCCTRL - 0x8020 03A8) */
typedef struct{
__REG32         :1;
__REG32 RDITHER :1;
__REG32         :1;
__REG32 RPD     :1;
__REG32         :1;
__REG32 LDITHER :1;
__REG32         :1;
__REG32 LPD     :1;
__REG32         :24;
} __dadcctrl_bits;

/* Decimator Control Register (DECCTRL - 0x8020 03AC) */
typedef struct{
__REG32 RGAIN     :8;
__REG32 LGAIN     :8;
__REG32           :1;
__REG32 DADC_INV  :1;
__REG32 DADC_MUTE :1;
__REG32 ENODCBF   :1;
__REG32 ENIDCBF   :1;
__REG32           :1;
__REG32 ENTIMER   :1;
__REG32           :9;
} __decctrl_bits;

/* Decimator status register (DECSTAT - 0x8020 03B0) Read Only */
typedef struct{
__REG32 MUTED  :1;
__REG32 OVFLO  :1;
__REG32        :30;
} __decstat_bits;

/* Dual DAC Control Register (DDACCTRL - 0x8020 0398) */
typedef struct{
__REG32 RGAIN     :8;
__REG32 LGAIN     :8;
__REG32 DEEMPH    :3;
__REG32 SMUTE     :1;
__REG32 MODE2FS   :2;
__REG32 ROLLOFF   :2;
__REG32 PSLOW     :1;
__REG32 DDAC_PD   :1;
__REG32 DDAC_INV  :1;
__REG32 SILDET_T  :2;
__REG32 ENSILDET  :1;
__REG32           :2;
} __ddacctrl_bits;

/* Dual DAC status register (DDACSTAT - 0x8020 039C) Read Only */
typedef struct{
__REG32 MUTED   :1;
__REG32 PDOWN   :1;
__REG32 RSILENT :1;
__REG32 LSILENT :1;
__REG32         :28;
} __ddacstat_bits;

/* Dual DAC Settings Register (DDACSET - 0x8020 03A0) */
typedef struct{
__REG32         :8;
__REG32 RDYNPON :1;
__REG32 LDYNPON :1;
__REG32 LBI_DWA :1;
__REG32 RBI_DWA :1;
__REG32         :20;
} __ddacset_bits;

/* Power Control register (MCIPower - address 0x8010 0000) */
typedef struct{
__REG32 CTRL      :2;
__REG32           :4;
__REG32 OPENDRAIN :1;
__REG32           :25;
} __mcipower_bits;

/* Clock Control register (MCIClock - address 0x8010 0004) */
typedef struct{
__REG32 CLKDIV   : 8;
__REG32 CLKENAB  : 1;
__REG32 PWRSAVE  : 1;
__REG32 BYPASS   : 1;
__REG32 WIDEBUS  : 1;
__REG32          :20;
} __mciclock_bits;

/* Command register (MCICommand - address 0x8010 000C) */
typedef struct{
__REG32 CMDINDEX   : 6;
__REG32 RESPONSE   : 1;
__REG32 LONGRSP    : 1;
__REG32 INTERRUPT  : 1;
__REG32 W8PEND     : 1;
__REG32 CPSM_EN    : 1;
__REG32            :21;
} __mcicommand_bits;

/* Command Response register (MCIRespCommand - address 0x8010 0010) */
typedef struct{
__REG32 RESPCMD  : 6;
__REG32          :26;
} __mcirespcmd_bits;

/* Data Control register (MCIDataCtrl - address 0x8010 002C) */
typedef struct{
__REG32 XFERENAB   : 1;
__REG32 DIRECTION  : 1;
__REG32 STREAMMODE : 1;
__REG32 DMAENABLE  : 1;
__REG32 BLOCKSIZE  : 4;
__REG32            :24;
} __mcidatactrl_bits;

/* Status register (MCIStatus - address 0x8010 0034) */
typedef struct{
__REG32 CMDCRCFAIL       : 1;
__REG32 DATACRCFAIL      : 1;
__REG32 CMDTIMEOUT       : 1;
__REG32 DATATIMEOUT      : 1;
__REG32 TXUNDERRUN       : 1;
__REG32 RXOVERRUN        : 1;
__REG32 CMDRESPEND       : 1;
__REG32 CMDSENT          : 1;
__REG32 DATAEND          : 1;
__REG32 STARTBITERR      : 1;
__REG32 DATABLOCKEND     : 1;
__REG32 CMDACTIVE        : 1;
__REG32 TXACTIVE         : 1;
__REG32 RXACTIVE         : 1;
__REG32 TXFIFOHALFEMPTY  : 1;
__REG32 RXFIFOHALFFULL   : 1;
__REG32 TXFIFOFULL       : 1;
__REG32 RXFIFOFULL       : 1;
__REG32 TXFIFOEMPTY      : 1;
__REG32 RXDATAAVLBL      : 1;
__REG32 TXDATAAVLBL      : 1;
__REG32 RXFIFOEMPTY      : 1;
__REG32                  :10;
} __mcistatus_bits;

/* Clear register (MCIClear - 0x8010 0038) */
typedef struct{
__REG32 CMDCRCFAILCLR    : 1;
__REG32 DATACRCFAILCLR   : 1;
__REG32 CMDTIMEOUTCLR    : 1;
__REG32 DATATIMEOUTCLR   : 1;
__REG32 TXUNDERRUNCLR    : 1;
__REG32 RXOVERRUNCLR     : 1;
__REG32 CMDRESPENDCLR    : 1;
__REG32 CMDSENTCLR       : 1;
__REG32 DATAENDCLR       : 1;
__REG32 STARTBITERRCLR   : 1;
__REG32 DATABLOCKENDCLR  : 1;
__REG32                  :21;
} __mciclear_bits;

/* Interrupt Mask registers (MCIMask0-1 - addresses 0x8010 003C, 0x8010 0040) */
typedef struct{
__REG32 Mask0  :1;
__REG32 Mask1  :1;
__REG32 Mask2  :1;
__REG32 Mask3  :1;
__REG32 Mask4  :1;
__REG32 Mask5  :1;
__REG32 Mask6  :1;
__REG32 Mask7  :1;
__REG32 Mask8  :1;
__REG32 Mask9  :1;
__REG32 Mask10 :1;
__REG32 Mask11 :1;
__REG32 Mask12 :1;
__REG32 Mask13 :1;
__REG32 Mask14 :1;
__REG32 Mask15 :1;
__REG32 Mask16 :1;
__REG32 Mask17 :1;
__REG32 Mask18 :1;
__REG32 Mask19 :1;
__REG32 Mask20 :1;
__REG32 Mask21 :1;
__REG32        :10;
} __mcimask0_bits;

/* FIFO Counter register (MCIFifoCnt - address 0x8010 0048) */
typedef struct{
__REG32 DATACOUNT  :15;
__REG32            :17;
} __mcififocnt_bits;

/* MCI Clock Enable register (MCICLKEN - 0x8000 502C) */
typedef struct{
__REG32 MCICLKEN :1;
__REG32          :31;
} __mciclken_bits;

/* LCD Control Register (LCDCTRL - 0x8010 3004) */
typedef struct{
__REG32         :1;
__REG32 LCDPS   :1;
__REG32 LCDMI   :1;
__REG32 LCDW84  :1;
__REG32 SCLKSEL :2;
__REG32 SSAMPL  :2;
__REG32 LCDCBSY :1;
__REG32 CBSENSE :1;
__REG32 LCDBSYN :3;
__REG32 LRSSEL  :1;
__REG32 CSPOLAR :1;
__REG32 ERPOLAR :1;
__REG32 MSFIRST :1;
__REG32         :15;
} __lcdctrl_bits;

/* LCD Status Register (LCDSTAT - 0x8010 3000) Read Only */
typedef struct{
__REG32 LCDFIFOMT :1;
__REG32 LCDFIFOH  :1;
__REG32 LCDOVER   :1;