iolpc2888.h

基于 Philips 公司的 ARM-7 使用之 uC/OS-II 作业系统,此例程是移植于 LPC-2888 上的应用,不同于一般的 Porting 其最主要是加入了支援 OS_View 观察器功能

} __pop_bits;

/* Interrupt Status Register (INTS - 0x8010 1FE0) */
typedef struct{
__REG32 DCTSINT   :1;
__REG32           :3;
__REG32 THREINT   :1;
__REG32 RXTOINT   :1;
__REG32 RXDAINT   :1;
__REG32 WAKEUPINT :1;
__REG32 ABEOINT   :1;
__REG32 ABTOINT   :1;
__REG32           :2;
__REG32 BREAKINT  :1;
__REG32 FEINT     :1;
__REG32 PEINT     :1;
__REG32 OEINT     :1;
__REG32           :16;
} __ints_bits;

/* Interrupt Clear Status Register (INTCS - 0x8010 1FE8) */
typedef struct{
__REG32 DCTSINTCLR   :1;
__REG32              :3;
__REG32 THREINTCLR   :1;
__REG32 RXTOINTCLR   :1;
__REG32              :1;
__REG32 WAKEUPINTCLR :1;
__REG32 ABEOINTCLR   :1;
__REG32 ABTOINTCLR   :1;
__REG32              :5;
__REG32 OEINTCLR     :1;
__REG32              :16;
} __intcs_bits;

/* Interrupt Set Status Register (INTSS - 0x8010 1FEC) */
typedef struct{
__REG32 DCTSINTSET   :1;
__REG32              :3;
__REG32 THREINTSET   :1;
__REG32 RXTOINTSET   :1;
__REG32              :1;
__REG32 WAKEUPINTSET :1;
__REG32 ABEOINTSET   :1;
__REG32 ABTOINTSET   :1;
__REG32              :5;
__REG32 OEINTSET     :1;
__REG32              :16;
} __intss_bits;

/* Transfer Length Register (DMA[0..7]Length - 0x8010 3808..38E8) */
typedef struct{
__REG32 LENGTH :12;
__REG32        :20;
} __dma0length_bits;

/* Channel Configuration Registers (DMA[0..7]Config - 0x8010 380C..38EC) */
typedef struct{
__REG32 DESTID          :5;
__REG32 SOURCEID        :5;
__REG32 SIZE            :2;
__REG32 SWAPENDIAN      :1;
__REG32 PCH             :3;
__REG32                 :1;
__REG32 PCHEN           :1;
__REG32 CIRCULARBUFFER  :1;
__REG32                 :13;
} __dma0config_bits;

/* Channel Enable Registers (DMA[0..7]Enab - 0x8010 3810..38F0) */
typedef struct{
__REG32 ENAB :1;
__REG32      :31;
} __dma0enab_bits;

/* Transfer Count Registers (DMA[0..7]Count - 0x8010 381C..38FC) */
typedef struct{
__REG32 COUNT :12;
__REG32       :20;
} __dma0count_bits;

/* Alternate Transfer Length Registers (DMA[0..7]AltLength - 0x8010 3A08..3A78) */
typedef struct{
__REG32 LENGTH :12;
__REG32        :20;
} __dma0altlength_bits;

/* Global Enable Register (DMA_Enable - 0x8010 3C00) */
typedef struct{
__REG32 EN_CH0 :1;
__REG32 EN_CH1 :1;
__REG32 EN_CH2 :1;
__REG32 EN_CH3 :1;
__REG32 EN_CH4 :1;
__REG32 EN_CH5 :1;
__REG32 EN_CH6 :1;
__REG32 EN_CH7 :1;
__REG32        :24;
} __dma_enable_bits;

/* Global Status and Clear Register (DMA_Stat - 0x8010 3C04) */
typedef struct{
__REG32 COMPLETE0 :1;
__REG32 HALF0     :1;
__REG32 COMPLETE1 :1;
__REG32 HALF1     :1;
__REG32 COMPLETE2 :1;
__REG32 HALF2     :1;
__REG32 COMPLETE3 :1;
__REG32 HALF3     :1;
__REG32 COMPLETE4 :1;
__REG32 HALF4     :1;
__REG32 COMPLETE5 :1;
__REG32 HALF5     :1;
__REG32 COMPLETE6 :1;
__REG32 HALF6     :1;
__REG32 COMPLETE7 :1;
__REG32 HALF7     :1;
__REG32           :14;
__REG32 SOFTINT   :1;
__REG32 ABORT     :1;
} __dma_stat_bits;

/* IRQ Mask Register (DMA_IRQMask - 0x8010 3C08) */
typedef struct{
__REG32 MASKCOMP0   :1;
__REG32 MASKHALF0   :1;
__REG32 MASKCOMP1   :1;
__REG32 MASKHALF1   :1;
__REG32 MASKCOMP2   :1;
__REG32 MASKHALF2   :1;
__REG32 MASKCOMP3   :1;
__REG32 MASKHALF3   :1;
__REG32 MASKCOMP4   :1;
__REG32 MASKHALF4   :1;
__REG32 MASKCOMP5   :1;
__REG32 MASKHALF5   :1;
__REG32 MASKCOMP6   :1;
__REG32 MASKHALF6   :1;
__REG32 MASKCOMP7   :1;
__REG32 MASKHALF7   :1;
__REG32             :14;
__REG32 MASKSOFTINT :1;
__REG32 MASKABORT   :1;
} __dma_irqmask_bits;

/* DMA Channel 3 External Enable Register (DMA3EXTEN - 0x8000 5048) */
typedef struct{
__REG32 EXTEN :1;
__REG32       :31;
} __dma3exten_bits;

/* I2C Receive/Transmit Register */
typedef union {
  //I2RX
  struct {
__REG32 RX  : 8;
__REG32     : 24;
  };
  //I2TX
  struct {
__REG32 TX    :8;
__REG32 START :1;
__REG32 STOP  :1;
__REG32       :22;
  };
} __i2rx_bits;

/* I2C Status Register (I2STS - 0x8002 0804) */
typedef struct{
__REG32 OCI    :1;
__REG32 AFI    :1;
__REG32 NAI    :1;
__REG32 DRMI   :1;
__REG32 DRSI   :1;
__REG32 ACTIVE :1;
__REG32 SCL    :1;
__REG32 SDA    :1;
__REG32 RFF    :1;
__REG32 RFE    :1;
__REG32 TFF    :1;
__REG32 TFE    :1;
__REG32 TFFS   :1;
__REG32 TFES   :1;
__REG32        :18;
} __i2sts_bits;

/* I2C Control Register (I2CTL - 0x8002 0808) */
typedef struct{
__REG32 OCIE      :1;
__REG32 AFIE      :1;
__REG32 NAIE      :1;
__REG32 DRMIE     :1;
__REG32 DRSIE     :1;
__REG32 RFFE      :1;
__REG32 RFNEE     :1;
__REG32 TFNFE     :1;
__REG32 I2RES     :1;
__REG32           :1;
__REG32 TFNFSE    :1;
__REG32           :21;
} __i2ctl_bits;

/* I2C Clock Divisor High Register (I2CLKHI - 0x8002 080C) */
typedef struct{
__REG32 CDH :15;
__REG32     :17;
} __i2clkhi_bits;

/* I2C Clock Divisor Low Register (I2CLKLO - 0x8002 0810) */
typedef struct{
__REG32 CDL :15;
__REG32     :17;
} __i2clklo_bits;

/* I2C Slave Address Register (I2ADR - 0x8002 0814) */
typedef struct{
__REG32 ADR  :7;
__REG32      :25;
} __i2adr_bits;

/* I2C Rx FIFO Level Register (I2RFL - 0x8002 0818) */
typedef struct{
__REG32  RLF :5;
__REG32      :27;
} __i2rfl_bits;

/* I2C Tx FIFO Level Register (I2TFL - 0x8002 081C) */
typedef struct{
__REG32  TLF :5;
__REG32      :27;
} __i2tfl_bits;

/* I2C Rx Byte Count Register (I2RXB - 0x8002 0820) */
typedef struct{
__REG32 RXB :7;
__REG32     :25;
} __i2rxb_bits;

/* I2C Tx Byte Count Register (I2TXB - 0x8002 0824) */
typedef struct{
__REG32 TXB :7;
__REG32     :25;
} __i2txb_bits;

/* I2C Slave Transmit Register (I2TXS - 0x8002 0828) */
typedef struct{
__REG32 TXS :8;
__REG32     :24;
} __i2txs_bits;

/* I2C Slave Tx FIFO Level Register (I2STFL - 0x8002 082C) */
typedef struct{
__REG32  STFL :5;
__REG32       :27;
} __i2stfl_bits;

/* A/D Control Register (ADCCON - 0x8000 2420) */
typedef struct{
__REG32 SELVREF :1;
__REG32 ADCENAB :1;
__REG32 CSCAN   :1;
__REG32 ADCSTRT :1;
__REG32 ADCBUSY :1;
__REG32         :27;
} __adccon_bits;

/* A/D Select Register (ADCSEL-0x8000 2424) */
typedef struct{
__REG32 SEL0 :4;
__REG32 SEL1 :4;
__REG32 SEL2 :4;
__REG32 SEL3 :4;
__REG32 SEL4 :4;
__REG32 SEL5 :4;
__REG32      :8;
} __adcsel_bits;

/* A/D Result Registers (ADCR5:0 - 0x8000 2400:2414) */
typedef struct{
__REG32 ADCR :10;
__REG32      :22;
} __adcr0_bits;

/* A/D Interrupt Enable Register (ADCINTE - 0x8000 2428) */
typedef struct{
__REG32 INTENAB :1;
__REG32         :31;
} __adcinte_bits;

/* A/D Interrupt Status Register (ADCINTS - 0x8000 242C) */
typedef struct{
__REG32 INTSTAT :1;
__REG32         :31;
} __adcints_bits;

/* A/D Interrupt Status Register (ADCINTC - 0x8000 2430) */
typedef struct{
__REG32 INTCLR :1;
__REG32        :31;
} __adcintc_bits;

/* A/D Power Down Register (ADCPD - 0x8000 5028) */
typedef struct{
__REG32 ADCPD :1;
__REG32       :31;
} __adcpd_bits;

/* USB Device Address Register (USBDevAdr - 0x8004 1000) */
typedef struct{
__REG32 DEVADDR :7;
__REG32 DEVEN   :1;
__REG32         :24;
} __usbdevadr_bits;

/* USB Mode Register (USBMode - 0x8004 100C) */
typedef struct{
__REG32 SOFTCT    :1;
__REG32 PWROFF    :1;
__REG32 WKUP      :1;
__REG32 GIE       :1;
__REG32 USBRESET  :1;
__REG32 GOSUSP    :1;
__REG32 SNDRSU    :1;
__REG32 CLKAON    :1;
__REG32           :24;
} __usbmode_bits;

/* USB Interrupt Enable Register (USBIntE - 0x8004 108C) */
typedef struct{
__REG32 BRESET  :1;
__REG32 SOF     :1;
__REG32 PSOF      :1;
__REG32 SUSP      :1;
__REG32 RESUME    :1;
__REG32 HS_STAT   :1;
__REG32 DMA       :1;
__REG32 EP0SETUP  :1;
__REG32           :24;
} __usbinte_bits;

/* USB Interrupt Status Register (USBIntStat - 0x8004 1094) */
typedef struct{
__REG32 BRESET    :1;
__REG32 SOF       :1;
__REG32 PSOF      :1;
__REG32 SUSP      :1;
__REG32 RESUME    :1;
__REG32 HS_STAT   :1;
__REG32 DMA       :1;
__REG32 EP0SETUP  :1;
__REG32           :24;
} __usbintstat_bits;

/* USB Interrupt Clear Register (USBIntClr - 0x8004 10AC) */
typedef struct{
__REG32 CLRBRESET   :1;
__REG32 CLRSOF      :1;
__REG32 CLRPSOF     :1;
__REG32 CLRSUSP     :1;
__REG32 CLRRESUME   :1;
__REG32 CLRHS_STAT  :1;
__REG32 CLRDMA      :1;
__REG32 CLREP0SETUP :1;
__REG32             :24;
} __usbintclr_bits;

/* USB Interrupt Set Register (USBIntSet - 0x8004 10B0) */
typedef struct{
__REG32 SETBRESET   :1;
__REG32 SETSOF      :1;
__REG32 SETPSOF     :1;
__REG32 SETSUSP     :1;
__REG32 SETRESUME   :1;
__REG32 SETHS_STAT  :1;
__REG32 SETDMA      :1;
__REG32 SETEP0SETUP :1;
__REG32             :24;
} __usbintset_bits;

/* USB Interrupt Priority Register (USBIntP - 0x8004 10B4) */
typedef struct{
__REG32 BRESET1   :1;
__REG32 SOF1      :1;
__REG32 PSOF1     :1;
__REG32 SUSP1     :1;
__REG32 RESUME1   :1;
__REG32 HS_STAT1  :1;
__REG32 UDMA1     :1;
__REG32 EP0SETUP1 :1;
__REG32           :24;
} __usbintp_bits;

/* USB Interrupt Configuration Register (USBIntCfg - 0x8004 1010) */
typedef struct{
__REG32 INTPOL      :1;
__REG32 INTEDGE     :1;
__REG32 DDBG_M_OUT  :2;
__REG32 DDBG_M_IN   :2;
__REG32 CDGB_M      :2;
__REG32             :24;
} __usbintcfg_bits;

/* USB Frame Number Register (USBFN - 0x8004 1074) */
typedef struct{
__REG32 SOF   :11;
__REG32 MSOF  :3;
__REG32       :18;
} __usbfn_bits;

/* USB Scratch Register (USBScratch - 0x8004 1078) */
typedef struct{
__REG32  SCRATCH :16;
__REG32          :16;
} __usbscratch_bits;

/* USB lock Register (USBlock - 0x8004 107C) */
typedef struct{
__REG32 UNLOCKCODE :16;
__REG32            :16;
} __usblock_bits;

/* USB Endpoint Index Register (USBEIX - 0x8004 102C) */
typedef struct{
__REG32 DIR        :1;
__REG32 ENDPIDX    :4;
__REG32 SEL_EP0SET :1;
__REG32            :26;
} __usbeix_bits;

/* USB Endpoint Type Register (USBEType - 0x8004 1008) */
typedef struct{
__REG32 TYPE    :2;
__REG32 DBLBUF  :1;
__REG32 EP_ENAB :1;
__REG32 DIS_EOT :1;
__REG32         :27;
} __usbetype_bits;

/* USB Endpoint Control Register (USBECtrl - 0x8004 1028) */
typedef struct{
__REG32 STALL     :1;
__REG32 TO_STATUS :1;
__REG32 DATA      :1;
__REG32           :1;
__REG32 CLRBUF    :1;
__REG32 BUFFULL   :1;
__REG32           :26;
} __usbectrl_bits;

/* USB Endpoint Max Packet Size Register (USBMaxSize - 0x8004 1004) */
typedef struct{
__REG32 FIFOSIZE :11;
__REG32 NTRANS   :2;
__REG32          :19;
} __usbmaxsize_bits;

/* USB Data Count Register (USBDCnt - 0x8004 101C) */
typedef struct{
__REG32 DATACOUNT :11;
__REG32           :21;
} __usbdcnt_bits;

/* USB Short Packet Register (USBShort - 0x8004 1024) */
typedef struct{
__REG32 OUTSH :8;
__REG32       :24;
} __usbshort_bits;

/* USB Endpoint Interrupt Enable Register (USBEIntE - 0x8004 1090) */
typedef struct{
__REG32 EP0RXIE :1;
__REG32 EP0TXIE :1;
__REG32 EP1RXIE :1;
__REG32 EP1TXIE :1;
__REG32 EP2RXIE :1;
__REG32 EP2TXIE :1;
__REG32 EP3RXIE :1;
__REG32 EP3TXIE :1;
__REG32 EP4RXIE :1;
__REG32 EP4TXIE :1;
__REG32 EP5RXIE :1;
__REG32 EP5TXIE :1;
__REG32 EP6RXIE :1;
__REG32 EP6TXIE :1;
__REG32 EP7RXIE :1;
__REG32 EP7TXIE :1;
__REG32         :16;
} __usbeinte_bits;

/* USB Endpoint Interrupt Status Register (USBEIntStat - 0x8004 1098) */
typedef struct{
__REG32 EP0RX :1;
__REG32 EP0TX :1;
__REG32 EP1RX :1;
__REG32 EP1TX :1;
__REG32 EP2RX :1;
__REG32 EP2TX :1;
__REG32 EP3RX :1;
__REG32 EP3TX :1;
__REG32 EP4RX :1;
__REG32 EP4TX :1;
__REG32 EP5RX :1;
__REG32 EP5TX :1;
__REG32 EP6RX :1;
__REG32 EP6TX :1;
__REG32 EP7RX :1;
__REG32 EP7TX :1;