iolpc2888.h

基于 Philips 公司的 ARM-7 使用之 uC/OS-II 作业系统,此例程是移植于 LPC-2888 上的应用,不同于一般的 Porting 其最主要是加入了支援 OS_View 观察器功能

} __emcdynamicrc_bits;

/* Dynamic Memory Auto-refresh Period Register (EMCDynamictRFC -
 * address 0x8000 804C) */
typedef struct{
__REG32 TRFC :5;
__REG32      :27;
} __emcdynamicrfc_bits;

/* Dynamic Memory Exit Self-refresh Register (EMCDynamictXSR -
 * address 0x8000 8050) */
typedef struct{
__REG32 TXSR :5;
__REG32      :27;
} __emcdynamicxsr_bits;

/* Dynamic Memory Active Bank A to Active Bank B Time Register(EMCDynamictRRD -
 * address 0x8000 8054) */
typedef struct{
__REG32 TRRD :4;
__REG32      :28;
} __emcdynamicrrd_bits;

/* Dynamic Memory Load Mode Register to Active Command Time(EMCDynamictMRD -
 * address 0x8000 8058) */
typedef struct{
__REG32 TMRD :4;
__REG32      :28;
} __emcdynamicmrd_bits;

/* Dynamic Memory Configuration Register (EMCDynamicConfig -
 * address 0x8000 8100) */
typedef struct{
__REG32           :3;
__REG32 MD        :2;
__REG32           :2;
__REG32 ADDR_MAP1 :6;
__REG32           :1;
__REG32 ADDR_MAP2 :1;
__REG32           :4;
__REG32 BUF_EN    :1;
__REG32 WP        :1;
__REG32           :11;
} __emcdynamicconfig_bits;

/* Dynamic Memory RAS/CAS Delay Register (EMCDynamicRasCas - 0x8000 8104) */
typedef struct{
__REG32 RAS :2;
__REG32     :6;
__REG32 CAS :2;
__REG32     :22;
} __emcdynamicrascas_bits;

/* Static Memory Configuration Registers (EMCStaticConfig0-2 -
   addresses 0x8000 8200, 0x8000 8220, 0x8000 8240) */
typedef struct{
__REG32 MW   :2;
__REG32      :1;
__REG32 PM   :1;
__REG32      :2;
__REG32 CSP  :1;
__REG32 BLS  :1;
__REG32 EXTW :1;
__REG32      :10;
__REG32 WBEN :1;
__REG32 WP   :1;
__REG32      :11;
} __emcstaticconfig0_bits;

/* Static Memory Write Enable Delay registers (EMCStaticWaitWen0-2 - addresses
0x8000 8204,0x8000 8224, 0x8000 8244) */
typedef struct{
__REG32 WAITWEN :4;
__REG32         :28;
} __emcstaticwaitwen0_bits;

/* Static Memory Output Enable Delay Registers (EMCStaticWaitOen0-2 - addresses
0x8000 8208, 0x8000 8228, 0x8000 8248) */
typedef struct{
__REG32 WAITOEN :4;
__REG32         :28;
} __emcstaticwaitoen0_bits;

/* Static Memory Read Delay Registers (EMCStaticWaitRd0-2 - addresses
0x8000 820C, 0x8000 822C, 0x8000 824C) */
typedef struct{
__REG32 WAITRD :5;
__REG32        :27;
} __emcstaticwaitrd0_bits;

/* Static Memory Page Mode Read Delay Registers 0-2 (EMCStaticWaitPage0-2 -
addresses 0x8000 8210, 0x8000 8230, 0x8000 8250) */
typedef struct{
__REG32 WAITPAGE :5;
__REG32          :27;
} __emcstaticwaitpage0_bits;

/* Static Memory Write Delay Registers 0-2 (EMCStaticWaitWr0-2 - addresses
0x8000 8214, 0x8000 8234, 0x8000 8254) */
typedef struct{
__REG32 WAITWR :5;
__REG32        :27;
} __emcstaticwaitwr0_bits;

/* Static Memory Turnaound Delay Registers 0-2 (EMCStaticWaitTurn0-2 - addresses
0x8000 8218, 0x8000 8238, 0x8000 8258) */
typedef struct{
__REG32 WAITTURN :4;
__REG32          :28;
} __emcstaticwaitturn0_bits;

/* Static Memory Extended Wait Register (EMCStaticExtendedWait - address
0x8000 8080) */
typedef struct{
__REG32 EXTENDEDWAIT :10;
__REG32              :22;
} __emcstaticextendedwait_bits;

/* EMC Miscellaneous Control Register (EMCMisc - address 0x8000 505C) */
typedef struct{
__REG32 SREFREQ     :1;
__REG32             :7;
__REG32 REL1CONFIG  :1;
__REG32             :23;
} __emcmisc_bits;

/* Interrupt Request Registers (INT_REQ1:19, 0x8030 0404 - 0x8030 0474) */
typedef struct{
__REG32 PRIO      :4;
__REG32           :4;
__REG32 TARGET    :1;
__REG32           :7;
__REG32 INTEN     :1;
__REG32 ACTVLO    :1;
__REG32           :7;
__REG32 WE_ACTVLO :1;
__REG32 WE_ENABLE :1;
__REG32 WE_TARGET :1;
__REG32 WE_PRIO   :1;
__REG32 CLR_SWINT :1;
__REG32 SET_SWINT :1;
__REG32 PENDING   :1;
} __int_req_bits;

/* Interrupt Pending Register (INT_PENDING - 0x8030 0200) */
typedef struct{
__REG32         :1;
__REG32 IRQ0    :1;
__REG32 IRQ1    :1;
__REG32 IRQ2    :1;
__REG32 IRQ3    :1;
__REG32 TIMER0  :1;
__REG32 TIMER1  :1;
__REG32 RTC     :1;
__REG32 ALARM   :1;
__REG32 ADC     :1;
__REG32 MCI0    :1;
__REG32 MCI1    :1;
__REG32 UART    :1;
__REG32 I2C     :1;
__REG32         :1;
__REG32         :1;
__REG32 SAI1    :1;
__REG32         :1;
__REG32         :1;
__REG32 SAI4    :1;
__REG32 SAO1    :1;
__REG32 SAO2    :1;
__REG32         :1;
__REG32 FLASHP  :1;
__REG32 LCD     :1;
__REG32 GPDMA   :1;
__REG32 USB0    :1;
__REG32 USB1    :1;
__REG32 USB2    :1;
__REG32 USB3    :1;
__REG32         :2;
} __int_pending_bits;

/* Vector Registers (INT_VECTOR0:1, 0x8030 0100 - 0x8030 0104) */
typedef struct{
__REG32             :3;
__REG32 INDEX       :5;
__REG32             :3;
__REG32 TABLE_ADDR  :21;
} __int_vector0_bits;

/* Priority Mask Registers (INT_PRIOMASK0:1, 0x8030 0000 - 0x8030 0004) */
typedef struct{
__REG32 PL  :4;
__REG32     :28;
} __int_priomask0_bits;

/* Features Register (INT_FEATURES - 0x8030 0300) */
typedef struct{
__REG32 SOURCES :8;
__REG32 PL      :8;
__REG32 TARGETS :6;
__REG32         :10;
} __int_features_bits;

/* Control registers (T0CTRL, T1CTRL - 0x8002 0008, 0x8002 0408) */
typedef struct{
__REG32           :2;
__REG32 PRESCALE  :2;
__REG32           :2;
__REG32 TMODE     :1;
__REG32 TENAB     :1;
__REG32           :24;
} __t0ctrl_bits;

/* Watchdog Status Register (WDT_SR - 0x8000 2800) */
typedef struct{
__REG32 MR0 :1;
__REG32 MR1 :1;
__REG32     :30;
} __wdt_sr_bits;

/* Watchdog Timer Control Register (WDT_TCR - 0x8000 2804) */
typedef struct{
__REG32 CE :1;
__REG32 CR :1;
__REG32    :30;
} __wdt_tcr_bits;

/* Watchdog Match Control Register (WDT_MCR - 0x8000 2814) */
typedef struct{
__REG32 E_MR0 :1;
__REG32 R_MR0 :1;
__REG32 S_MR0 :1;
__REG32 E_MR1 :1;
__REG32 R_MR1 :1;
__REG32 S_MR1 :1;
__REG32       :26;
} __wdt_mcr_bits;

/* Watchdog External Match Register (WDT_EMR - 0x8000 283C) */
typedef struct{
__REG32 M0  :1;
__REG32     :3;
__REG32 EI  :2;
__REG32     :1;
__REG32 ER  :1;
__REG32     :24;
} __wdt_emr_bits;

/* RTC Configuration Register (RTC_CFG - 0x8000 5024) */
typedef struct{
__REG32 PWR_UP :1;
__REG32        :31;
} __rtc_cfg_bits;

/* Interrupt Location Register (ILR - address 0x8000 2000) */
typedef struct{
__REG32 RTCCIF :1;
__REG32 RTCALF :1;
__REG32        :30;
} __ilr_bits;

/* Clock Tick Counter Register (CTCR - address 0x8000 2004) */
typedef struct{
__REG32 CTC :15;
__REG32     :17;
} __ctc_bits;

/* Clock Control Register (CCR - address 0x8000 2008) */
typedef struct{
__REG32 CLKEN   :1;
__REG32 CTCRST  :1;
__REG32 CTTEST  :2;
__REG32         :28;
} __ccr_bits;

/* Counter Increment Interrupt Register (CIIR - address 0x8000 200C) */
typedef struct{
__REG32 IMSEC   :1;
__REG32 IMMIN   :1;
__REG32 IMHOUR  :1;
__REG32 IMDOM   :1;
__REG32 IMDOW   :1;
__REG32 IMDOY   :1;
__REG32 IMMON   :1;
__REG32 IMYEAR  :1;
__REG32         :24;
} __ciir_bits;

/* Alarm Mask Register (AMR - address 0x8000 2010) */
typedef struct{
__REG32 AMRSEC  :1;
__REG32 AMRMIN  :1;
__REG32 AMRHOUR :1;
__REG32 AMRDOM  :1;
__REG32 AMRDOW  :1;
__REG32 AMRDOY  :1;
__REG32 AMRMON  :1;
__REG32 AMRYEAR :1;
__REG32         :24;
} __amr_bits;

/* Consolidated Time register 0 (CTIME0 - address 0x8000 2014) */
typedef struct{
__REG32 SECONDS :6;
__REG32         :2;
__REG32 MINUTES :6;
__REG32         :2;
__REG32 HOURS   :5;
__REG32         :3;
__REG32 DOW     :3;
__REG32         :5;
} __ctime0_bits;

/* Consolidated Time register 1 (CTIME1 - address 0x8000 2018) */
typedef struct{
__REG32 DOM   :5;
__REG32       :3;
__REG32 MONTH :4;
__REG32       :4;
__REG32 YEAR  :12;
__REG32       :4;
} __ctime1_bits;

/* Consolidated Time register 2 (CTIME2 - address 0x8000 201C) */
typedef struct{
__REG32 DOY :12;
__REG32     :20;
} __ctime2_bits;

/* RTC second register */
typedef struct{
__REG32 SEC  : 6;
__REG32      :26;
} __sec_bits;

/* RTC minute register */
typedef struct{
__REG32 MIN  : 6;
__REG32      :26;
} __min_bits;

/* RTC hour register */
typedef struct{
__REG32 HOUR  : 5;
__REG32       :27;
} __hour_bits;

/* RTC day of month register */
typedef struct{
__REG32 DOM  : 5;
__REG32      :27;
} __dom_bits;

/* RTC day of week register */
typedef struct{
__REG32 DOW  : 3;
__REG32      :29;
} __dow_bits;

/* RTC day of year register */
typedef struct{
__REG32 DOY  : 9;
__REG32      :23;
} __doy_bits;

/* RTC month register */
typedef struct{
__REG32 MON  : 4;
__REG32      :28;
} __month_bits;

/* RTC year register */
typedef struct{
__REG32 YEAR  :12;
__REG32       :20;
} __year_bits;

/* Interrupt Enable Register (IER - 0x8010 1004 when DLAB=0) */

typedef union {
  // IER
  struct{
__REG32 RDAINTEN  :1;
__REG32 THREINTEN :1;
__REG32 RLSINTEN  :1;
__REG32 MSINTEN   :1;
__REG32           :3;
__REG32 CTSINTEN  :1;
__REG32 ABEOINTEN :1;
__REG32 ABTOINTEN :1;
__REG32           :22;
  };
  // DLM
  struct{
__REG32 _DLM :8;
__REG32     :24;
  };
} __ier_bits;

/* Interrupt Identification Register (IIR - 0x8010 1008, read only) */
typedef union{
  /*IIR*/
  struct{
__REG32 IS      :1;
__REG32 II      :3;
__REG32         :2;
__REG32 FE      :2;
__REG32 ABEOINT :1;
__REG32 ABTOINT :1;
__REG32         :22;
  };
/*FCR*/
  struct{
__REG32 FE2     :1;
__REG32 RXFR    :1;
__REG32 TXFR    :1;
__REG32 DMAMODE :1;
__REG32         :2;
__REG32 RXTL    :2;
__REG32         :24;
  };
} __iir_bits;

/* Line Control Register (LCR - 0x8010 100C) */
typedef struct{
__REG32 WLS   :2;
__REG32 SBS   :1;
__REG32 PE    :1;
__REG32 PS    :2;
__REG32 BC    :1;
__REG32 DLAB  :1;
__REG32       :24;
} __lcr_bits;

/* Modem Control Register (MCR - address 0x8010 1010) */
typedef struct{
__REG32         :1;
__REG32 RTS     :1;
__REG32         :2;
__REG32 LBMS    :1;
__REG32         :1;
__REG32 AUTORTS :1;
__REG32 AUTOCTS :1;
__REG32         :24;
} __mcr_bits;

/* Line Status Register (LSR - 0x8010 1014, read only) */
typedef struct{
__REG32 RDR   :1;
__REG32 OE    :1;
__REG32 PE    :1;
__REG32 FE    :1;
__REG32 BI    :1;
__REG32 THRE  :1;
__REG32 TEMP  :1;
__REG32 RXFE  :1;
__REG32       :24;
} __lsr_bits;

/* Modem Status Register (MSR - 0x8010 1018, Read Only) */
typedef struct{
__REG32 DTCS :1;
__REG32      :3;
__REG32 CTS  :1;
__REG32      :27;
} __msr_bits;

/* Scratch Pad Register (SCR - 0x8010 101C) */
typedef struct{
__REG32 PAD :8;
__REG32     :24;
} __scr_bits;

/* Auto-baud Control Register (ACR - 0x8010 1020) */
typedef struct{
__REG32 ACR_START   :1;
__REG32 ACR_MODE    :1;
__REG32 AUTORESTART :1;
__REG32             :6;
__REG32 ABEOINTCLR  :1;
__REG32 ABTOINTCLR  :1;
__REG32             :21;
} __acr_bits;

/* IrDA Control Register (ICR - 0x8010 1024) */
typedef struct{
__REG32 IRDAEN      :1;
__REG32 IRDAINV     :1;
__REG32 FIXPULSEEN  :1;
__REG32 PULSEDIV    :3;
__REG32             :26;
} __icr_bits;

/* Fractional Divider Register (FDR - 0x8010 1028) */
typedef struct{
__REG32 DIVADDVAL :4;
__REG32 MULVAL    :4;
__REG32           :24;
} __fdr_bits;

/* NHP Mode Register (MODE - 0x8010 1034) */
typedef struct{
__REG32 NHP :1;
__REG32     :31;
} __mode_bits;

/* NHP Pop Register (POP - 0x8010 1030) */
typedef struct{
__REG32 POP :1;
__REG32     :31;