iolpc2888.h

基于 Philips 公司的 ARM-7 使用之 uC/OS-II 作业系统,此例程是移植于 LPC-2888 上的应用,不同于一般的 Porting 其最主要是加入了支援 OS_View 观察器功能

/***************************************************************************
 **
 **    This file defines the Special Function Registers for
 **    LPC2888
 **
 **    Used with ICCARM and AARM.
 **
 **    (c) Copyright IAR Systems 2006
 **
 **    $Revision: 1.0 $
 **
 **    Note: Only little endian addressing of registers.
 ***************************************************************************/

#ifndef __IOLPC2888_H
#define __IOLPC2888_H

#if (((__TID__ >> 8) & 0x7F) != 0x4F)     /* 0x4F = 79 dec */
#error This file should only be compiled by ICCARM/AARM
#endif

#include "io_macros.h"

/***************************************************************************
 ***************************************************************************
 **
 **   LPC2888 SPECIAL FUNCTION REGISTERS
 **
 ***************************************************************************
 ***************************************************************************
 ***************************************************************************/


/* C specific declarations  ************************************************/

#ifdef __IAR_SYSTEMS_ICC__

#ifndef _SYSTEM_BUILD
#pragma system_include
#endif

#if __LITTLE_ENDIAN__ == 0
#error This file should only be compiled in little endian mode
#endif

/* Boot Map register (SYS_BOOTMAP - 0x8000 5070) */
typedef struct{
__REG32 MAP   :1;
__REG32       :31;
} __sys_bootmap_bits;

/* Boot Address register (SYS_BOOTADDR - 0x8000 5074) */
typedef struct{
__REG32           :10;
__REG32 BOOTADDR  :22;
} __sys_bootaddr_bits;

/* Cache Reset Status register (CACHE_RST_STAT, 0x8010 4000) */
typedef struct{
__REG32 CACHE_STATUS :1;
__REG32              :31;
} __cache_rst_stat_bits;

/* Cache Settings register (CACHE_SETTINGS, 0x8010 4004) */
typedef struct{
__REG32 CACHE_RST          :1;
__REG32 DATA_ENABLE        :1;
__REG32 INSTRUCTION_ENABLE :1;
__REG32 PERF_ANAL_RST      :1;
__REG32 PERF_ANAL_ENA      :1;
__REG32                    :27;
} __cache_settings_bits;

/* Cache Page Enable Control register (CACHE_PAGE_CTRL,0x8010 4008) */
typedef struct{
__REG32 PAGE_0_ENA  :1;
__REG32 PAGE_1_ENA  :1;
__REG32 PAGE_2_ENA  :1;
__REG32 PAGE_3_ENA  :1;
__REG32 PAGE_4_ENA  :1;
__REG32 PAGE_5_ENA  :1;
__REG32 PAGE_6_ENA  :1;
__REG32 PAGE_7_ENA  :1;
__REG32 PAGE_8_ENA  :1;
__REG32 PAGE_9_ENA  :1;
__REG32 PAGE_10_ENA :1;
__REG32 PAGE_11_ENA :1;
__REG32 PAGE_12_ENA :1;
__REG32 PAGE_13_ENA :1;
__REG32 PAGE_14_ENA :1;
__REG32 PAGE_15_ENA :1;
__REG32             :16;
} __cache_page_ctrl_bits;

/* Address Pointer for Page(n) registers (ADDRESS_PAGE_(n),0x8010 4018) */
typedef struct{
__REG32 UPPR_ADDR :11;
__REG32           :21;
} __address_page_n_bits;

/* CPU Clock Gate control (CPU_CLK_GATE, 0x8010 4058) */
typedef struct{
__REG32 CPU_CLK_GATE :1;
__REG32              :31;
} __cpu_clk_gate_bits;

/* Flash Control register (F_CTRL-0x8010 2000) */
typedef struct{
__REG32 FC_CS       :1;
__REG32 FC_FUNC     :1;
__REG32 FC_WEN      :1;
__REG32             :2;
__REG32 FC_RD_LATCH :1;
__REG32             :1;
__REG32 FC_PROTECT  :1;
__REG32             :2;
__REG32 FC_SET_DATA :1;
__REG32 FC_RSSL     :1;
__REG32 FC_PROG_REQ :1;
__REG32             :1;
__REG32 FC_CLR_BUF  :1;
__REG32 FC_LOAD_REQ :1;
__REG32             :16;
} __f_ctrl_bits;

/* Flash Status register (F_STAT - 0x8010 2004) */
typedef struct{
__REG32 FS_DONE     :1;
__REG32 FS_PROGGNT  :1;
__REG32 FS_RDY      :1;
__REG32             :2;
__REG32 FS_ERR      :1;
__REG32             :26;
} __f_stat_bits;

/* Flash Program Time register (F_PROG_TIME - 0x8010 2008) */
typedef struct{
__REG32 FPT_TIME    :15;
__REG32 FPT_ENABLE  :1;
__REG32             :16;
} __f_prog_time_bits;

/* Flash Wait States register (F_WAIT - 0x8010 2010) */
typedef struct{
__REG32 WAIT_STATES :8;
__REG32             :24;
} __f_wait_bits;

/* Flash Clock Divider register (F_CLK_TIME - 0x8010 201C) */
typedef struct{
__REG32 CLK_DIV :12;
__REG32         :20;
} __f_clk_time_bits;

/* Flash Interrupt Status register (F_INT_STAT - 0x8010 2FE0) */
typedef struct{
__REG32 END_OF_ERASE    :1;
__REG32 END_OF_PROGRAM  :1;
__REG32                 :30;
} __f_int_stat_bits;

/* Flash Interrupt Set register (F_INT_SET - 0x8010 2FEC) */
typedef struct{
__REG32 SET_INT :2;
__REG32         :30;
} __f_int_set_bits;

/* Flash Interrupt Clear register (F_INT_CLR - 0x8010 2FE8) */
typedef struct{
__REG32 CLR_INT :2;
__REG32         :30;
} __f_int_clr_bits;

/* Flash Interrupt Enable register (F_INTEN - 0x8010 2FE4) */
typedef struct{
__REG32 EOE_ENABLE  :1;
__REG32 EOP_ENABLE  :1;
__REG32             :30;
} __f_inten_bits;


/* Flash Interrupt Enable Set register (F_INTEN_SET - 0x8010 2FDC) */
typedef struct{
__REG32 SET_ENABLE  :2;
__REG32             :30;
} __f_inten_set_bits;

/* Flash Interrupt Enable Clear register (F_INTEN_CLR - 0x8010 2FD8) */
typedef struct{
__REG32 CLR_ENABLE :2;
__REG32            :30;
} __f_inten_clr_bits;

/* Flash Power Down register (FLASH_PD - 0x8000 5030) */
typedef struct{
__REG32 FLASH_PD :1;
__REG32          :31;
} __flash_pd_bits;

/* Flash Initialization register (FLASH_INIT - 0x8000 5034) */
typedef struct{
__REG32 FLASH_INIT :1;
__REG32            :31;
} __flash_init_bits;

/* DCDC converter 1 Adjustment register (DCDCADJUST1 - address 0x8000 5004) */
typedef struct{
__REG32 DCDCADJUST1 :3;
__REG32             :29;
} __dcdcadjust1_bits;

/* DCDC converter 2 Adjustment register (DCDCADJUST2 - address 0x8000 5008) */
typedef struct{
__REG32 DCDCADJUST2 :3;
__REG32             :29;
} __dcdcadjust2_bits;

/* DCDC Clock Select register (DCDCCLKSEL - address 0x8000 500C) */
typedef struct{
__REG32 DCDCCLKSEL  :1;
__REG32             :31;
} __dcdcclksel_bits;

/* Power Mode Register (PMODE-0x8000 4C00) */
typedef struct{
__REG32 CGUMODE :2;
__REG32         :30;
} __pmode_bits;

/* WatchDog Bark Register (WDBARK - 0x8000 4C04) */
typedef struct{
__REG32 BARK :1;
__REG32      :31;
} __wdbark_bits;

/* 32 kHz Oscillator Control (OSC32EN - 0x8000 4C08) */
typedef struct{
__REG32 RUN :1;
__REG32     :31;
} __osc32en_bits;

/* Main Oscillator Control (OSCEN - 0x8000 4C10) */
typedef struct{
__REG32 RUN :1;
__REG32     :31;
} __oscen_bits;

/* Input Select Register (HPFIN - 0x8000 00AC) */
typedef struct{
__REG32 HPSELECT  :4;
__REG32           :28;
} __hpfin_bits;

/* Initial Divider Control Register (HPNDEC - 0x8000 00B4) */
typedef struct{
__REG32 NDEC :10;
__REG32      :22;
} __hpndec_bits;

/* Multiplier Control Register (HPMDEC - 0x8000 00B0) */
typedef struct{
__REG32 MDEC :17;
__REG32      :15;
} __hpmdec_bits;

/* Final Divider Control Register (HPPDEC - 0x8000 00B8) */
typedef struct{
__REG32 PDEC :7;
__REG32      :25;
} __hppdec_bits;

/* Mode Register (HPMODE - 0x8000 00BC) */
typedef struct{
__REG32 HPCLKEN :1;
__REG32         :1;
__REG32 HPPD    :1;
__REG32         :1;
__REG32 DIRECTI :1;
__REG32 FREERUN :1;
__REG32         :26;
} __hpmode_bits;

/* Status Register (HPSTAT - 0x8000 00C0) */
typedef struct{
__REG32 HPLOCK  :1;
__REG32 HPFREE  :1;
__REG32         :30;
} __hpstat_bits;

/* Rate Change Request Register (HPREQ - 0x8000 00C8) */
typedef struct{
__REG32 HPMREQ :1;
__REG32 HPNREQ :1;
__REG32 HPPREQ :1;
__REG32        :29;
} __hpreq_bits;

/* Rate Change Acknowledge Register (HPACK - 0x8000 00C4) */
typedef struct{
__REG32 HPMACK :1;
__REG32 HPNACK :1;
__REG32 HPPACK :1;
__REG32        :29;
} __hpack_bits;

/* R Bandwidth Register (HPSELR - 0x8000 00D8) */
typedef struct{
__REG32 SELR :4;
__REG32      :28;
} __hpselr_bits;

/* I Bandwidth Register (HPSELI - 0x8000 00DC) */
typedef struct{
__REG32 SELI :4;
__REG32      :28;
} __hpseli_bits;

/* P Bandwidth Register (HPSELP - 0x8000 00E0) */
typedef struct{
__REG32 SELP :5;
__REG32      :27;
} __hpselp_bits;

/* Switch Configuration Registers (SYSSCR-DAISCR; 0x8000 4000-4024) */
typedef struct{
__REG32 ENF1   :1;
__REG32 ENF2   :1;
__REG32 SCRES  :1;
__REG32 SCSTOP :1;
__REG32        :28;
} __sysscr_daiscr_bits;

/* Frequency Select 1 Registers (SYSFSR1-DAIFSR1; 0x8000 402C-4050) */
typedef struct{
__REG32 SELECT :4;
__REG32        :28;
} __sysfsr1_daifsr1_bits;

/* Switch Status Registers (SYSSSR-DAISSR; 0x8000 4084-40A8) */
typedef struct{
__REG32 ENF1    :1;
__REG32 ENF2    :1;
__REG32 SELECT  :4;
__REG32         :26;
} __sysssr_daissr_bits;

/* Base Control Registers (SYSBCR-DAIOBCR; 0x8000 43F0-43F8) */
typedef struct{
__REG32 FDRUN :1;
__REG32       :31;
} __sysbcr_daiobcr_bits;

/* Fractional divider configuration registers */
typedef struct{
__REG32 FDRUN   :1;
__REG32 FDRES   :1;
__REG32 FDSTRCH :1;
__REG32 MADD    :8;
__REG32 MSUB    :8;
__REG32         :13;
} __sysfdcr_bits;

/* Fractional divider configuration registers */
typedef struct{
__REG32 FDRUN   :1;
__REG32 FDRES   :1;
__REG32 FDSTRCH :1;
__REG32 MADD    :10;
__REG32 MSUB    :10;
__REG32         :9;
} __daiofdcr4_bits;

/* Power control register bit descriptions */
typedef struct{
__REG32 PCRUN     :1;
__REG32 PCAUTO    :1;
__REG32 WAKE_EN   :1;
__REG32 EXTEN_EN  :1;
__REG32 ENOUT_EN  :1;
__REG32           :27;
} __power_control_bits;

/* Power status register bit descriptions */
typedef struct{
__REG32 PSACTIVE :1;
__REG32 PSWAKE   :1;
__REG32          :30;
} __power_status_bits;

/* Enable select registers with 1 bit fields */
typedef struct{
__REG32 ESR_EN  :1;
__REG32 ESR_SEL :1;
__REG32         :30;
} __enable_select1_bits;

/* Enable select registers with 3 bit fields */
typedef struct{
__REG32 ESR_EN  :1;
__REG32 ESR_SEL :3;
__REG32         :28;
} __enable_select3_bits;

/* Enable select registers with none bit field */
typedef struct{
__REG32 ESR_EN :1;
__REG32        :31;
} __enable_select_none_bits;

/* EMC Control Register (EMCControl - address 0x8000 8000) */
typedef struct{
__REG32 MPMC      :1;
__REG32 AM        :1;
__REG32 LPM       :1;
__REG32           :29;
} __emccontrol_bits;

/* EMC Status Register (EMCStatus - address 0x8000 8004) */
typedef struct{
__REG32 BUSY  :1;
__REG32 WBS   :1;
__REG32 SRACK :1;
__REG32       :29;
} __emcstatus_bits;

/* EMC Configuration Register (EMCConfig - address 0x8000 8008) */
typedef struct{
__REG32 BIGENDIAN  :1;
__REG32            :7;
__REG32 CLKOUTDIV2 :1;
__REG32            :23;
} __emcconfig_bits;

/* Dynamic Control Register (EMCDynamicControl - address 0x8000 8020) */
typedef struct{
__REG32 FORCE_CKE    :1;
__REG32 FORCE_CLKOUT :1;
__REG32 SRREQ        :1;
__REG32              :2;
__REG32 MMC          :1;
__REG32              :1;
__REG32 SDRAMINI     :2;
__REG32              :4;
__REG32 DP           :1;
__REG32 RPOUT        :2;
__REG32              :16;
} __emcdynamiccontrol_bits;

/* Dynamic Memory Refresh Timer Register (EMCDynamicRefresh - 0x8000 8024) */
typedef struct{
__REG32 REFRESH :11;
__REG32         :21;
} __emcdynamicrefresh_bits;

/* Dynamic Memory Read Configuration Register (EMCDynamicReadConfig -
 * address 0x8000 8028) */
typedef struct{
__REG32 RDS :2;
__REG32     :30;
} __emcdynamicreadconfig_bits;

/* Dynamic Memory Percentage Command Period Register (EMCDynamictRP -
 * address 0x8000 8030) */
typedef struct{
__REG32 TRP :4;
__REG32     :28;
} __emcdynamicrp_bits;

/* Dynamic Memory Active to Precharge Command Period Register
(EMCDynamictRAS - address 0x8000 8034) */
typedef struct{
__REG32 TRAS :4;
__REG32      :28;
} __emcdynamicras_bits;

/* Dynamic Memory Self-refresh Exit Time Register (EMCDynamictSREX -
 * address 0x8000 8038) */
typedef struct{
__REG32 TSREX :4;
__REG32       :28;
} __emcdynamicsrex_bits;

/* Memory Last Data Out to Active Time Register (EMCDynamictAPR -
 * address 0x8000 803C) */
typedef struct{
__REG32 TAPR :4;
__REG32      :28;
} __emcdynamicapr_bits;

/* Dynamic Memory Data-in to Active Command Time Register (EMCDynamictDAL -
 * address 0x8000 8040) */
typedef struct{
__REG32 TDAL :4;
__REG32      :28;
} __emcdynamicdal_bits;

/* Dynamic Memory Write recover Time Register (EMCDynamictWR -
 * address 0x8000 8044) */
typedef struct{
__REG32 TWR :4;
__REG32     :28;
} __emcdynamicwr_bits;

/* Dynamic Memory Active to Active Command Period Register (EMCDynamictRC -
 * address 0x8000 8048) */
typedef struct{
__REG32 TRC :5;
__REG32     :27;