⭐ 欢迎来到虫虫下载站! | 📦 资源下载 📁 资源专辑 ℹ️ 关于我们
⭐ 虫虫下载站

📄 bsp.c

📁 基于 Philips 公司的 ARM-7 使用之 uC/OS-II 作业系统,此例程是移植于 LPC-2888 上的应用,不同于一般的 Porting 其最主要是加入了支援 OS_View 观察器功能
💻 C
📖 第 1 页 / 共 4 页
字号:
*
* Argument(s): led      The id of the LED to turn OFF.  For this board, the only valid value is 1.
*
* Returns    : None
*
*********************************************************************************************************
*/

void  LED_Off (CPU_INT08U led)
{
    if (led == 1) {
        MODE1S_2 = BSP_LED;
        MODE0S_2 = BSP_LED;
    }
}


/*
******************************************************************************************************************************
*                                           PB SERVICES
******************************************************************************************************************************
*/

/*
*********************************************************************************************************
*                                      GET PUSH BUTTON STATUS
*
* Description: This function returns the status of the specified push button.
*
* Argument(s): pb      The id of the PB.
*
* Returns    : DEF_TRUE     if the push button is down.
*              DEF_FALSE    if the push button is up or if the push button id specified is invalid.
*********************************************************************************************************
*/

CPU_BOOLEAN  PB_GetStatus (CPU_INT08U pb)
{
    switch (pb) {
        case 1:
             if (PINS_2 & BSP_PB1) {
                 return (DEF_TRUE);
             }
             break;
        case 2:
             if (PINS_2 & BSP_PB2) {
                 return (DEF_TRUE);
             }
             break;
    }

    return (DEF_FALSE);
}


/*
******************************************************************************************************************************
*                                             ADC SERVICES
******************************************************************************************************************************
*/
/*
*********************************************************************************************************
*                                             GET AD STATUS
*
* Description: This function returns the status of the specified push button.
*
* Argument(s): adc     The id of the A/D.
*
* Returns    : A 10-bit integer, between 0x0000 and 0x03FF.  This ratio of this integer to 0x03FF is equal
*              to the ratio between the analog input voltage and the reference voltage.  Essentially,
*
*                       Va = Vref * (ret / 0x03FF)
*
*              where Va is the analog input voltage, Vref is the reference voltage, and ret is the
*              return value of the function.
*********************************************************************************************************
*/

CPU_INT16U  ADC_GetStatus (CPU_INT08U adc)
{
    CPU_INT16U  result;


    result = 0;

    switch (adc) {
        case 0:
             result = ADCR0 & 0x03FF;
             break;
        case 1:
             result = ADCR1 & 0x03FF;
             break;
        default:
             break;
    }

    return (result);
}


/*
******************************************************************************************************************************
*                                           uC/OS-View SERVICES
******************************************************************************************************************************
*/

/*
*********************************************************************************************************
*                                     INITIALIZE TIMER FOR uC/OS-View
*
* Description: This function is called to by uC/OS-View to initialize the free running timer that is
*              used to make time measurements.
*
* Argument(s): None
*
* Returns    : None
*********************************************************************************************************
*/

#if OS_VIEW_MODULE > 0
void  OSView_TmrInit (void)
{
    T1CTRL         = 0;                                         /* Disable timer 1                                          */
    T1CTRL         = 0x80;                                      /* Prescaler set to no division; enable timer 1             */
}
#endif

/*
*********************************************************************************************************
*                                     READ TIMER FOR uC/OS-View
*
* Description: This function is called to read the current counts of a 32 bit free running timer.
*
*               Timer #0 of the LPC2000 is used.  This is a DOWN-timer.
*
* Argument(s): None
*
* Returns    : The 32 bit counts of the timer assuming the timer (MUST be an UP counter).
*
* Note(s)    : (1) Since the timer counts DOWN, the complement of the value in the timer register
*                  is returned
*********************************************************************************************************
*/

#if OS_VIEW_MODULE > 0
CPU_INT32U  OSView_TmrRd (void)
{
    if (OSRunning == DEF_TRUE) {
        return ((CPU_INT32U)(~T1VALUE));
    } else {
        return (0);
    }
}
#endif

/*
*********************************************************************************************************
*                                 SET INTERRUPT VECTOR FOR uC/OS-View
*
* Description: This function sets the timer interrupt vector for uC/OS-View.
*
* Argument(s): None.
*
* Returns    : None.
*
* Caller(s)  : OSView_InitTarget()
*********************************************************************************************************
*/

#if OS_VIEW_MODULE > 0
void  OSView_IntInit (void)
{
    BSP_IntInstall(VIC_UART, OSView_RxTxISRHandler, 5);
}
#endif


/*
******************************************************************************************************************************
*                                             LOCAL FUNCTIONS
******************************************************************************************************************************
*/

/*
*********************************************************************************************************
*                                          SETUP THE CGU
*
* Description: This function sets up and activates the Clock Generation Unit.
*
* Arguments  : None
*
* Returns    : None
*
* Notes      : (1) The main oscillator will be set to (CLK_OSC_FREQ)*(MSEL + 1) = (12 MHz) * 4 = 48 MHz
*
*              (2) Using the frequency divider, a clock must be set up for the LCD.  Two fields are set:
*                  MSUB, which is -n; and MADD, which is m - n.  The resultant clock frequency will be
*
*                    CLKIN * n
*                    ---------
*                        m
*
*                  In this case, MSUB = -16 = 0xF0; MADD = 112 = 0x70.  The frequency will be
*                  48 MHz * -MSUB / (MADD - MSUB) = 48 MHz * 16 / 128 = 6 MHz.
*
*             (3)  Using a frequency divider, a clock is also setup for the MMC/SD card interface.  The
*                  fields, MSUB and MADD, are set to 0xE7 and 0x17, respectively, for an output frequency
*                  of 25 MHz.
*********************************************************************************************************
*/

static  void  BSP_CGU_Init (void)
{
    LPPDN     = 0x00000001;                                     /* Power down the main PLL                                  */
    LPFIN     = 0x00000001;                                     /* Select main oscillator as PLL's input clock              */
    LPMSEL    = 0x00000003;                                     /* Multiply input clock by (2 + 1) = 4                      */
    LPPSEL    = 0x00000001;                                     /* Make CCO equal to 4 times PLL output                     */
    LPPDN     = 0x00000000;                                     /* Power up the main PLL                                    */

    while (LPLOCK == 0x00000000) {                              /* Wait for PLL to lock                                     */
        ;
    }
                                                                /* Choose clocks for the  selection stages                   */
    SYSFSR1   = CGU_FSR_MAIN_PLL;                               /* Select PLL    for SYS  selection stage                    */
    SYSSCR    = CGU_SCR_ENF1;                                   /* Select side 1 for SYS  selection stage                    */
    APB0FSR1  = CGU_FSR_MAIN_PLL;                               /* Select PLL    for APB0 selection stage                    */
    APB0SCR   = CGU_SCR_ENF1;                                   /* Select side 1 for APB0 selection stage                    */
    APB1FSR1  = CGU_FSR_MAIN_PLL;                               /* Select PLL    for APB1 [timer] selection stage            */
    APB1SCR   = CGU_SCR_ENF1;                                   /* Select side 1 for APB1 [timer] selection stage            */
    UARTFSR1  = CGU_FSR_MAIN_PLL;                               /* Select PLL    for UART selection stage                    */
    UARTSCR   = CGU_SCR_ENF1;                                   /* Select side 1 for UART selection stage                    */

    APB3FSR1  = CGU_FSR_MAIN_PLL;
    APB3SCR   = CGU_SCR_ENF1;
    DCDCFSR1  = CGU_FSR_MAIN_PLL;
    DCDCSCR   = CGU_SCR_ENF1;
    RTCFSR1   = CGU_FSR_MAIN_PLL;
    RTCSCR    = CGU_SCR_ENF1;
    MCIFSR1   = CGU_FSR_MAIN_PLL;
    MCISCR    = CGU_SCR_ENF1;
    DAIOFSR1  = CGU_FSR_MAIN_PLL;
    DAIOSCR   = CGU_SCR_ENF1;
    DAISFSR1  = CGU_FSR_MAIN_PLL;
    DAISCR    = CGU_SCR_ENF1;

                                                                /* Setup SYS Fractional Divider #1 for LCD clcok            */
    SYSFDCR1 &= ~CGU_FDCR_FDRUN;                                /* Stop the fractional divider                              */
    SYSFDCR1  = ((BSP_SYSFSR1_MSUB << 11)                       /* Set MSUB = -n                                            */
              |  (BSP_SYSFSR1_MADD << 3)                        /* Set MADD = m - n                                         */
              |   CGU_FDCR_FDSTRCH                              /* Enable stretch                                           */
              |   CGU_FDCR_FDRES);                              /* Reset fractional divider                                 */
    SYSFDCR1 &= ~CGU_FDCR_FDRES;                                /* Clear reset bit                                          */
    SYSFDCR1 |=  CGU_FDCR_FDRUN;                                /* Restart the fractional divider                           */

                                                                /* Setup SYS Fractional Divider #2 for SD/MCI clcok         */
    SYSFDCR2 &= ~CGU_FDCR_FDRUN;                                /* Stop the fractional divider                              */
    SYSFDCR2  = ((BSP_SYSFSR2_MSUB << 11)                       /* Set MSUB = -n                                            */
              |  (BSP_SYSFSR2_MADD << 3)                        /* Set MADD = m - n                                         */
              |   CGU_FDCR_FDSTRCH                              /* Enable stretch                                           */
              |   CGU_FDCR_FDRES);                              /* Reset fractional divider                                 */
    SYSFDCR2 &= ~CGU_FDCR_FDRES;                                /* Clear reset bit                                          */
    SYSFDCR2 |=  CGU_FDCR_FDRUN;                                /* Restart the fractional divider                           */

                                                                /* Setup APB Fractional Divider #0 for ADC clcok            */
    APB0FDCR0 &= ~CGU_FDCR_FDRUN;                               /* Stop the fractional divider                              */
    APB0FDCR0  = ((BSP_APB0FSR0_MSUB << 11)                     /* Set MSUB = -n                                            */
              |  (BSP_APB0FSR0_MADD << 3)                       /* Set MADD = m - n                                         */
              |   CGU_FDCR_FDSTRCH                              /* Enable stretch                                           */
              |   CGU_FDCR_FDRES);                              /* Reset fractional divider                                 */
    APB0FDCR0 &= ~CGU_FDCR_FDRES;                               /* Clear reset bit                                          */
    APB0FDCR0 |=  CGU_FDCR_FDRUN;                               /* Restart the fractional divider                           */


                                                                /* Choose clocks for spreading stages under SYS             */
    APB0ESR0  = CGU_ESR_SSCLOCK;                                /* Select spreading stage clock for APB0                    */
    APB1ESR0  = CGU_ESR_SSCLOCK;                                /* Select spreading stage clock for APB1                    */
    APB2ESR   = CGU_ESR_SSCLOCK;                                /* Select spreading stage clock for APB2                    */
    APB3ESR0  = CGU_ESR_SSCLOCK;                                /* Select spreading stage clock for APB3                    */
    AHB0ESR   = CGU_ESR_SSCLOCK;                                /* Select spreading stage clock for USB                     */
    USBESR0   = CGU_ESR_SSCLOCK;                                /* Select spreading stage clock for USB                     */
    LCDESR1   = CGU_ESR_FD1;                                    /* Select LCD bus clock from fractional divider 1           */
    LCDESR0   = CGU_ESR_SSCLOCK;                                /* Select spreading stage clock for LCD PCLK                */
    MCIESR1   = CGU_ESR_FD2;                                    /* Select MCI bus clock from fractional divider 2           */
    MCIESR0   = CGU_ESR_SSCLOCK;                                /* Select spreading stage clock for MCI PCLK                */
    DMAESR1   = CGU_ESR_SSCLOCK;                                /* Select spreading stage clock for DMA PCLK                */
    DMAESR0   = CGU_ESR_SSCLOCK;                                /* Select spreading stage clock for DMA channels            */

                                                                /* Choose clocks for spreading stages under APB0            */
    ADCESR1   = CGU_ESR_FD0;                                    /* Select ADC bus clock from fractional divider 0           */
    ADCESR0   = CGU_ESR_SSCLOCK;                                /* Select spreading stage clock for ADC PCLK                */

                                                                /* Choose clocks for spreading stages under APB1            */
    T0ESR     = CGU_ESR_SSCLOCK;                                /* Select spreading stage clock for Timer #0                */
    T1ESR     = CGU_ESR_SSCLOCK;                                /* Select spreading stage clock for Timer #1                */

                                                                /* Choose clocks for spreading stages under UART            */
    UARTESR1  = CGU_ESR_SSCLOCK;                                /* Select spreading stage clock for UART                    */

    SYSBCR    = CGU_BCR_FDRUN;                                  /* Start fractional dividers                                */
    APB0BCR   = CGU_BCR_FDRUN;                                  /* Start fractional dividers                                */
}

/*
*********************************************************************************************************
*                                     INITIALIZE THE CACHE CONTROLLER
*
* Description: This function caches the lower portion of RAM at 0x00000000 so the interrupt
*              vector table may be referenced.
*
* Argument(s): None
*
* Returns    : None
*********************************************************************************************************
*/

static  void  BSP_Cache_Init (void)
{
    CACHE_SETTINGS = 0x00000001;                                /* Reset the cache                                          */
    CACHE_SETTINGS = 0x00000000;                                /* De-assert reset to cache controller                      */

    while ((CACHE_RST_STAT) & 0x00000001) {                     /* Wait for reset to complete                               */
        ;
    }

    CACHE_PAGE_CTRL = 0x00000001;                               /* Enable virtual page 0                                    */
    ADDRESS_PAGE_0  = (0x400000 >> 21);                         /* Prepare virtual address for RAM                          */
    CACHE_SETTINGS  = 0x00000016;                               /* Enable caching                                           */
}

/*
*********************************************************************************************************
*                                      PUSH BUTTON INITIALIZATION
*
* Description: This function initializes the push buttons as input pins.
*
* Argument(s): none
*
* Returns    : none
*********************************************************************************************************
*/

⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -