sys_init.c

ADI的ADSP-BF561下实现多媒体开发的通用框架。

#include <services/services.h>
#include <ezkitutilities.h>
#include <drivers/adi_dev.h>
#include <drivers/ppi/adi_ppi.h>
#include "..\Buffer.h"
#include "core.h"


/*********************************************************************

	Function:		ExceptionHandler
					HWErrorHandler

	Description:	We should never get an exception or hardware error, 
					but just in case we'll catch them and simply turn 
					on all the LEDS should one ever occur.

*********************************************************************/

static ADI_INT_HANDLER(ExceptionHandler)	// exception handler
{
		ezErrorCheck(1);
		return(ADI_INT_RESULT_PROCESSED);
}
		
	
static ADI_INT_HANDLER(HWErrorHandler)		// hardware error handler
{
		ezErrorCheck(1);
		return(ADI_INT_RESULT_PROCESSED);
}


//sys_init
sys_init()
{

	u32 			ResponseCount;		// response counter
	ADI_PWR_COMMAND_PAIR ezkit_power[] = {
    { ADI_PWR_CMD_SET_PROC_VARIANT,			(void*)ADI_PWR_PROC_BF561SKBCZ600X }, // 600Mhz ADSP-BF561 variant
    { ADI_PWR_CMD_SET_PACKAGE,     			(void*)ADI_PWR_PACKAGE_MBGA        }, // in MBGA packaging, as on all EZ-KITS
    { ADI_PWR_CMD_SET_VDDEXT,      			(void*)ADI_PWR_VDDEXT_330          }, // external voltage supplied to the voltage regulator is 3.3V
    { ADI_PWR_CMD_SET_CLKIN,       			(void*)ADI_PWR_CLKIN_EZKIT_BF561   },
    { ADI_PWR_CMD_SET_AUTO_SYNC_ENABLED, 	(void*)NULL						   }, 	// the CLKIN frequency 25 Hz
    { ADI_PWR_CMD_END,             			0                          		   }
	};
	
	
	ADI_EBIU_SDRAM_BANK_VALUE bank_size;
	ADI_EBIU_SDRAM_BANK_VALUE bank_width;
	u32                       cl_threshold = 100;                                        // set cl threshold to 100 Mhz
	ADI_EBIU_TIMING_VALUE     twrmin       = {1,{7500, ADI_EBIU_TIMING_UNIT_PICOSEC}};   // set min TWR to 1 SCLK cycle + 7.5ns
	ADI_EBIU_TIMING_VALUE     refresh      = {8192,{64, ADI_EBIU_TIMING_UNIT_MILLISEC}}; // set refresh period to 8192 cycles in 64ms
	ADI_EBIU_TIME             trasmin      = {44, ADI_EBIU_TIMING_UNIT_NANOSEC};         // set min TRAS to 44ns
	ADI_EBIU_TIME             trpmin       = {20, ADI_EBIU_TIMING_UNIT_NANOSEC};	     // set min TRP to 20ns
	ADI_EBIU_TIME             trcdmin      = {20, ADI_EBIU_TIMING_UNIT_NANOSEC}; 	     // set min TRCD to 20ns
	bank_size.value.size                   = ADI_EBIU_SDRAM_BANK_64MB; 	                 // set bank size to 64MB
	bank_width.value.width                 = ADI_EBIU_SDRAM_BANK_COL_10BIT;	             // set column address width to 10-Bit

	ADI_EBIU_COMMAND_PAIR ezkit_sdram[] = {
		{ ADI_EBIU_CMD_SET_SDRAM_BANK_SIZE,     (void*)&bank_size   },
       	{ ADI_EBIU_CMD_SET_SDRAM_BANK_COL_WIDTH,(void*)&bank_width  },
       	{ ADI_EBIU_CMD_SET_SDRAM_CL_THRESHOLD,  (void*)cl_threshold },
      	{ ADI_EBIU_CMD_SET_SDRAM_TRASMIN,       (void*)&trasmin     },
       	{ ADI_EBIU_CMD_SET_SDRAM_TRPMIN,        (void*)&trpmin      },
       	{ ADI_EBIU_CMD_SET_SDRAM_TRCDMIN,       (void*)&trcdmin     },
       	{ ADI_EBIU_CMD_SET_SDRAM_TWRMIN,        (void*)&twrmin      },
       	{ ADI_EBIU_CMD_SET_SDRAM_REFRESH,       (void*)&refresh     },
      	{ ADI_EBIU_CMD_END,                     0                   }
	};		
		
	
	
	//adi_pwr_SetMaxFreqForVolt(ADI_PWR_VLEV_120);
	// initialize the Interrupt Manager 
	ezErrorCheck(adi_int_Init(IntMgrData, sizeof(IntMgrData), &ResponseCount, NULL));

	// enable core B to run (not necessary with VisualDSP debugger,
	// but is necessary when booting from or executing from external memory.
//	*pSICA_SYSCR &= 0xFFDF;	
	
	adi_pwr_SetFreq(594,118,ADI_PWR_DF_NONE);
	
	ButtonPressed = FALSE;

 //	adi_pwr_SetFreq(0,0,ADI_PWR_DF_NONE);
 	
	// hook the exception and hardware error interrupts
	ezErrorCheck(adi_int_CECHook(3, ExceptionHandler, NULL, FALSE));
	ezErrorCheck(adi_int_CECHook(5, HWErrorHandler, NULL, FALSE));
	
	// initialize the Deferred Callback Manager and setup a queue
#if defined(USE_DEFERRED_CALLBACKS)
	ezErrorCheck(adi_dcb_Init(&DCBMgrData[0], ADI_DCB_QUEUE_SIZE, &ResponseCount, NULL));
	ezErrorCheck(adi_dcb_Open(14, &DCBMgrData[ADI_DCB_QUEUE_SIZE], (ADI_DCB_ENTRY_SIZE)*4, &ResponseCount, &DCBManagerHandle));
#else
	DCBManagerHandle = NULL;
#endif

	// initialize the DMA Manager
	ezErrorCheck(adi_dma_Init(DMAMgrData, sizeof(DMAMgrData), &ResponseCount, &DMAManagerHandle, NULL));
	
	// initialize the Device Manager
	ezErrorCheck(adi_dev_Init(DevMgrData, sizeof(DevMgrData), &ResponseCount, &DeviceManagerHandle, NULL));
	
	*pDMA1_TC_PER=0x77f0;
	*pDMA2_TC_PER=0x77f0;
	*pEBIU_AMGCTL|=0x0100;
}