📄 adv7183.h
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// AUTHOR: JC DATE:AUG 18TH, 2003
// Modified by GJO Oct 28
#ifndef _ADV7183
#define _ADV7183
#define ADV7183WR 0x40
#define ADV7183RD 0x41
//#define ADV7183WR 0x8A //if ALSB =1
//#define ADV7183RD 0x8B
enum DECODER { INPUT_CONTROL_REGISTER=0x00,
VIDEO_SELECTION_REGISTER,
VIDEO_ENHANCEMENT_CONTROL_REGISTER,
OUTPUT_CONTROL_REGISTER,
EXTENDED_OUTPUT_CONTROL_REGISTER,
GENERAL_PURPOSE_OUTPUT_REGISTER,
RESERVE0,
FIFO_CONTROL_REGISTER,
CONTRAST_REGISTER,
SATURATION_REGISTER,
BRIGHTNESS_REGISTER,
HUE_REGISTER,
DEFAULT_Y_REGISTER,
DEFAULT_C_REGISTER,
TEMPERAL_DECIMATION_REGISTER,
POWER_MANAGEMENT_REGISTER,
STATUS_REGISTER,
INFO_REGISTER,
RESERVE1,
ANALOG_CONTROL_INTERNAL_REGISTER,
ANALOG_CLAMP_CONTROL_REGISTER,
DIGITAL_CLAMP_CONTROL_1_REGISTER,
DIGITAL_CLAMP_CONTROL_2_REGISTER,
SHAPING_FILTER_CONTROL_REGISTER,
RESERVE2,
COMB_FILTER_CONTROL_REGISTER,
COLOR_SOBCARRIER_CONTROL_1_REGISTER=0x23,
COLOR_SOBCARRIER_CONTROL_2_REGISTER,
COLOR_SOBCARRIER_CONTROL_3_REGISTER,
COLOR_SOBCARRIER_CONTROL_4_REGISTER,
PIXEL_DELAY_CONTROL_REGISTER,
MANUAL_CLOCK_CONTROL_1_REGISTER,
MANUAL_CLOCK_CONTROL_2_REGISTER,
MANUAL_CLOCK_CONTROL_3_REGISTER,
AUTO_CLOCK_CONTROL_REGISTER,
AGC_MODE_CONTROL_REGISTER,
CHROMA_GAIN_CONTROL_1_REGISTER,
CHROMA_GAIN_CONTROL_2_REGISTER,
LUMA_GAIN_CONTROL_1_REGISTER,
LUMA_GAIN_CONTROL_2_REGISTER,
MANUAL_GAIN_SHADOW_CONTROL_1_REGISTER,
MANUAL_GAIN_SHADOW_CONTROL_2_REGISTER,
MISCELLANEOUS_GAIN_CONTROL_REGISTER,
HSYNC_POSITION_CONTROL_1_REGISTER,
HSYNC_POSITION_CONTROL_2_REGISTER,
HSYNC_POSITION_CONTROL_3_REGISTER,
POLARITY_REGISTER,
RESAMPLE_CONTROL_REGISTER=0x44,
};
//Input Control Register
#define CVBS_AVIN1 0x00
#define CVBS_AVIN2 0x01
#define CVBS_AVIN3 0x02
#define CVBS_AVIN4 0x03
#define CVBS_AVIN5 0x04
#define CVBS_AVIN6 0x05
#define Y_AVIN1_C_AVIN4 0x06
#define Y_AVIN2_C_AVIN5 0x07
#define Y_AVIN3_C_AVIN6 0x08
#define Y_AVIN1_U_AVIN4_V_AVIN5 0x09
#define Y_AVIN2_U_AVIN3_V_AVIN6 0x0A
#define AUTO_NO_PEDESTAL 0x00
#define AUTO_PEDESTAL 0x10
#define AUTO_PAL_N_NTSC_M_NO_PEDESTAL 0x20
#define AUTO_PAL_N_NTSC_M_PEDESTAL 0x30
#define NTSC_M_NO_PEDESTAL 0x40
#define NTSC_M_PEDESTAL 0x50
#define NTSC_443_NO_PEDESTAL 0x60
#define NTSC_443_PEDESTAL 0x70
#define PAL_BGHID_NO_PEDESTAL 0x80
#define PAL_N_PEDESTAL 0x90
#define PAL_M_NO_PEDESTAL 0xA0
#define PAL_M_PEDESTAL 0xB0
#define PAL_COMBINATION_N 0xC0
#define PAL_COMBINATION_N_PEDESTAL 0xD0
//Video Selection REgister
#define BROADCAST_QUALITY 0x00
#define TV_QUALITY 0x01
#define VCR_QUALITY 0x02
#define SURVEILLANCE_QUALITY 0x03
#define STANDARD_MODE 0x00
#define SQUARE_PIXEL_MODE 0x04
#define SINGLE_ENDED_INPUTS 0x00
#define DIFFERENTIAL_INPUTS 0x08
#define STANDARD_VIDEO_OPERATION 0x00
#define FOUR_FSC_MODE 0x10
#define STANDARD_VIDEO_INPUT 0x00
#define BETACAM_INPUT 0x20
#define NO_REACQUIRE 0x80
#define RECQUIRE 0x00
//Video Enhancement Control Register
#define C_4P5DB_S_9P25DB 0x00
#define C_4P5DB_S_9P25DB_2 0x01
#define C_4P5DB_S_5P75DB 0x02
#define C_1P25DB_S_3P3DB 0X03
#define C_0DB_S_0DB 0X04
#define C_N1P25DB_S_N3DB 0X05
#define C_N1P75DB_S_N8DB 0X06
#define C_N3DB_S_N8DB 0X07
#define NO_CORING 0X00
#define TRUNCATE_BLACK_PLUS8 0X08
#define TRUNCATE_BLACK_PLUS16 0X10
#define TRUNCATE_BLACK_PLUS32 0X18
//Output Control Register
#define PHILLIPS_COMPATIBLE 0X00
#define BROKTREE_A_COMPATIBLE 0X01
#define BROKTREE_B_COMPATIBLE 0X02
#define LLC_422_10BIT 0X00
#define LLC2_422_20BIT 0X04
#define LLC2_422_16BIT 0X08
#define LLC_422_8BIT 0X0C
#define LLC2_411_12BIT 0X10
#define OE_PIN_DEPENDENT 0X00
#define OE_PIN_INDEPENDENT 0X40
#define ALL_LINES_FILTERED 0X00
#define FILTER_ACTIVE_VIDEO_ONLY 0X80
//EXTEND OUTPUT CONTROL REGISTER
#define CCIR_COMPLIANT 0X00
#define FILL_WHOLE_RANGE 0X01
#define BT656_3_COMPATIBLE 0X00
#define BT656_4_COMPATIBLE 0X80
//GENERAL PURPOSE OUTPUT REGISTER
#define GPO_1_0_THREE_STATED 0X00
#define GPO_1_0_ENABLED 0X10
#define GPO_3_2_THREE_STATED 0X00
#define GPO_3_2_ENABLED 0X20
#define OUTPUT_CHROMA_AT_VBI 0X00
#define BLANK_CHROMA_AT_VBI 0X40
#define GPO_0_PIN_FUNCTION 0X00
#define GPO_0_HLOCK_STATUS 0X80
//FIFO CONTROL REGISTER
#define NORMAL_OPERATION 0X00
#define FIFO_RESET 0X20
#define NO_AUTO_RESET 0X00
#define AUTO_RESET 0X40
#define SYNC_CLKIN 0X00
#define SYNC_27MHZ 0X80
//SATUARION REGISTER
#define SAT_NEGATIVE_42DB 0X00
#define SAT_0DB 0X80
#define SAT_6DB 0XFF
//BRIGHTNESS REGISTER
#define BRIGH_0DB 0X00
#define BRIGHT_3DB 0X7F
#define BRIGHT_NEGATIVE_3DB 0X80
//HUE REGISTER
#define ZERO_DEGREE 0X00
#define NINTY_DEGREE 0X7F
#define NEGATIVE_NINTY 0X80
//TEMPERAL DECIMATION REGISTER
#define TDE_DISABLED 0X00
#define TDE_ENABLED 0X01
#define START_EVEN_FIELD 0X00
#define START_ODD_FIELD 0X02
#define SUPRESS_EVEN_FIELD 0X04
#define SUPPRESS_ODD_FIELD 0X06
#define SKIP_NONE 0X00
#define SKIP_1_FIELD 0X08
#define SKIP_2_FIELD 0X10
#define SKIP_3_FIELD 0X18
#define SKIP_4_FIELD 0X20
#define SKIP_5_FIELD 0X28
#define SKIP_6_FIELD 0X30
#define SKIP_7_FIELD 0X38
#define SKIP_8_FIELD 0X40
#define SKIP_9_FIELD 0X48
#define SKIP_10_FIELD 0X50
#define SKIP_11_FIELD 0X58
#define SKIP_12_FIELD 0X60
#define SKIP_13_FIELD 0X68
#define SKIP_14_FIELD 0X70
#define SKIP_15_FIELD 0X78
//POWER MAMAGEMENT REGISTER
#define FULL_OPERATION 0X00
#define CVBS_INPUT_ONLY 0X01
#define DIGITAL_ONLY 0X02
#define POWER_SAVE_MODE 0X03
#define POWER_DOWN_BY_PIN 0X00
#define POWER_DOWN_BY_BIT 0X04
#define REFERENCE_FUNCTIONAL 0X00
#define REFERENCE_IN_POWER_SAVE_MODE 0X08
#define CLOCK_GEN_FUNCTIONAL 0X00
#define CLOCK_GEN_POWER_SAVE_MODE 0X10
#define SYSTEM_FUNCTION 0X00
#define POWER_DOWN 0X20
#define REACQUIRE_VIDEO_SIGNAL 0X40
#define RESET_DIGITAL_CORE_AND_I2C 0X80
//ANALOG CONTROL INTERNAL REGISTER
#define OE_AND_TOD_DEPENDENT 0X00
#define HS_VS_F_FORCED_ACTIVE 0X02
//ANALOG CLAMP CONTROL REGISTER
#define FINE_CLAMP_16CYCLES 0X00
#define FINE_CLAMP_32CYCLES 0X01
#define FINE_CLAMP_64CYCLES 0X02
#define FINE_CLAMP_128CYCLES 0X03
#define FAST_CLAMP_16CYCLES 0X00
#define FAST_CLAMP_32CYCLES 0X04
#define FAST_CLAMP_64CYCLES 0X08
#define FAST_CLAMP_128CYCLES 0X0C
#define I_OFF 0X00
#define I_ON 0X10
#define VOLTAGE_CLAMP_OFF 0X00
#define VOLTAGE_CLAMP_ON 0X20
//DIGITAL CLAMP CONTROL 1 REGISTER
#define DIGITAL_CLAMP_OPERATIONAL 0X00
#define DIGITAL_CLAMP_FROZEN 0X10
#define DCT_SLOW 0X00
#define DCT_MEDIUM 0X20
#define DCT_FAST 0X40
#define DCT_VID_QUAL_DEPENDENT 0X60
#define AUTOMATIC_DIGITAL_CLAMP 0X00
#define MANUAL_OFFSET_CORRECTION 0X80
//SHAPING FILTER CONTROL REGISTER
#define AUTO_WIDE_NOTCH 0X00
#define AUTO_NARROW_NOTCH 0X01
#define SVHS1 0X02
#define SVHS17 0X12
#define PALNN1 0X13
#define PALNN2 0X14
#define PALNN3 0X15
#define PALWN1 0X16
#define PALWN2 0X17
#define NTSCNN1 0X18
#define NTSCNN2 0X19
#define NTSCNN3 0X1A
#define NTSCWN1 0X1B
#define NTSCWN2 0X1C
#define NTSCWN3 0X1D
#define SVHS18 0X1F
#define AUTO_1P5MHZ 0X00
#define AUTO_2P17MHZ 0X20
#define SH1 0X40
#define SH2 0X60
#define SH5 0XC0
#define SH6 0XE0
//COMB FILTER CONTROL REGISTER
#define CCM_1H 0X04
#define CCM_2H 0X08
#define COMB_NONADAPTIVE 0X00
#define COMB_ADAPTIVE 0X10
//COLOR SUBCARRIER CONTROL 1 REGISTER
#define MANUAL_FSC 0X10
//PIXEL DELAY CONTROL REGISTER
#define CHROMA_2PIXEL_EARLY 0X08
#define CHROMA_1PIXEL_EARLY 0X10
#define NO_DELAY 0X18
#define CHROMA_1PIXEL_LATE 0X20
#define CHROMA_2PIXEL_LATE 0X28
#define CHROMA_3PIXEL_LATE 0X30
#define DELAY_RESERVE 0X40
#define SWAP_CR_CB 0X80
//MANUAL CLOCK CONTROL 1 REGISTER
#define FREQ_FOLLOWS_VIDEO 0X00
#define FREQ_FOLLOWS_CLKVAL 0X40
#define FREQ_FOLLOWS_CLOCKGEN 0X00
#define OUTPUT_27MHZ 0X80
//AUTO CLOCK CONTROL REGISTER
#define START_LINE_24_COLORBURST 0X20
#define ACTIVE_VIDEO 0X40
#define ACTIVE_VIDEO_304_PAL_264NTSC 0X60
#define ACTIVE_VIDEO_304_PAL_256NTSC 0X80
#define ACTIVE_VIDEO_304_PAL_274NTSC 0XA0
//AGC MODE CONTROL REGISTER
#define MANUAL_CMG 0X00
#define LUMA_GAIN_FOR_CHROMA 0X01
#define AUTO_GAIN 0X02
#define FREEZE_CHROMA_GAIN 0X03
#define MANUAL_LMG 0X00
#define NO_OVERRIDE_THRU_WHITEPEAK 0X10
#define AUTO_OVERRIDE_THRU_WHITEPEAK 0X20
#define NO_OVERRIDE_THRU_WHITEPEAK_2 0X30
#define AUTO_OVERRIDE_THRU_WHITEPEAK_2 0X40
#define AGC_ACTIVE_VIDEO_WHITE_PEAK 0X50
#define AGC_ACTIVE_VIDEO_AVERAGE_VIDEO 0X60
#define FREEZE_LUMA_GAIN 0X70
//CHROMA GAIN COMTROL 1 REGISTER
#define CHROMA_AUTOGAIN_SLOW 0X00
#define CHROMA_AUTOGAIN_MEDIUM 0X40
#define CHROMA_AUTOGAIN_FAST 0X80
#define CHROMA_GAIN_VID_QUAL_DEPENDENT 0XC0
//LUMA GAIN COMTROL 1 REGISTER
#define LUMA_AUTOGAIN_SLOW 0X00
#define LUMA_AUTOGAIN_MEDIUM 0X40
#define LUMA_AUTOGAIN_FAST 0X80
#define LUMA_GAIN_VID_QUAL_DEPENDENT 0XC0
//MISCELLANEOUS GAIN CONTROL REGISTER
#define UPDATE_ONCE_PER_LINE 0X00
#define UPDATE_ONCE_PER_FIELD 0X01
#define LINES_33_TO_310 0x00
#define LINES_33_to_270 0x02
#define PAL133_NTSC122 0X00
#define PAL125_NTSC115 0X04
#define PAL120_NTSC110 0X08
#define PAL115_NTSC105 0X0C
#define PAL110_NTSC100 0X10
#define PAL105_NTSC100 0X14
#define PAL100_NTSC100 0X18
#define COLOR_KILL_DISABLED 0X00
#define COLOR_KILL_ENABLED 0X40
//POLARITY REGISTER
#define PCLK_ACTIVE_HIGH 0X00
#define PCLK_ACTIVE_LOW 0X01
#define PFF_ACTIVE_HIGH 0X00
#define PFF_ACTIVE_LOW 0X02
#define PDV_ACTIVE_HIGH 0X00
#define PDV_ACTIVE_LOW 0X04
#define PF_ACTIVE_HIGH 0X00
#define PF_ACTIVE_LOW 0X08
#define PLLCR_ACTIVE_HIGH 0X00
#define PLLCR_ACTIVE_LOW 0X10
#define PVS_ACTIVE_HIGH 0X00
#define PVS_ACTIVE_LOW 0X20
#define PHVR_ACTIVE_HIGH 0X00
#define PHVR_ACTIVE_LOW 0X40
#define PHS_ACTIVE_HIGH 0X00
#define PHS_ACTIVE_LOW 0X80
//***** CONFIGURATION TABLE FOR ADC ADV7183 REGISTERS *****/
volatile int ADC_Config[56] = {
0x04, // INPUT CONTROL. CVBS in AIN5. Auto w/o pedestal
0x88, // VIDEO SELECTION. Differential mode. INSEL doesnot cause reaquire
0x04, // VIDEO ENHANCEMENT CONTROL. C=0, S=0 (Contrast and Saturation unaffected)
0x0C, // OUTPUT CONTROL. 8 bits @ LLC (Line Locked Clock) 4:2:2 CCIR656
0x0C, // EXTENDED OUTPUT CONTROL.
0x40, // GENERAL-PURPOSE OUTPUT.
0x00, // RESERVED
0x04, // FIFO CONTROL. User Programmable
0x80, // CONTRAST CONTROL.
0x80, // SATURATION CONTROL. 0dB
0x00, // BRIGHTNESS CONTROL. 0dB
0x00, // HUE CONTROL. 0deg
0x10, // DEFAULT VALUE Y. Default value
0x88, // DEFAULT VALUE C. Default value
0x00, // TEMPORAL DECIMATION. Disable
0x00, // POWER MANAGEMENT. Full operation
0x01, // STATUS REGISTER.
0x05, // INFO REGISTER
0x00, // RESERVED
0x45, // ANALOG CONTROL INTERNAL. Timing Signals o/p
0x18, // ANALOG CLAMP CONTROL
0x6F, // DIGITAL CLAMP CONTROL 1
0xFF, // DIGITAL CLAMP CONTROL 2
0x7D, // SHAPING FILTER CONTROL. Y shaping - NTSC WN3. C shaping SH2
0x00, // RESERVED
0x04, // COMB FILTER CONTROL. Chroma Comb mode 1H
0x00, // RESERVED
0x00, // RESERVED
0x00, // RESERVED
0x00, // RESERVED
0x00, // RESERVED
0x00, // RESERVED
0x00, // RESERVED
0x00, // RESERVED
0x00, // RESERVED
0xEF, // COLOR SUBCARRIER CONTROL 1. Manual Subcarrier freq disabled
0xFE, // COLOR SUBCARRIER CONTROL 2. No effect (Subcarrier manual freq)
0xFF, // COLOR SUBCARRIER CONTROL 3
0xFF, // COLOR SUBCARRIER CONTROL 4
0x58, // PIXEL DELAY CONTROL. No delay Chroma. No Cr Cb swapping
0x3F, // MANUAL CLOCK CONTROL 1. O/P freq set by video. Output 27MHz via LLC, LLC2 and LLCREF
0xFF, // MANUAL CLOCK CONTROL 2. Dont CAre
0xFF, // MANUAL CLOCK CONTROL 3. Dont CAre
0xA0, // AUTO CLOCK CONTROL. Active Video (<319/320)PAL and (<273/274) NTSC
0xCE, // AGC MODE CONTROL. Automatic Gain based on Chroma Burst. AGC override thro White Peaks.
0xFF, // CHROMA GAIN CONTROL 1. Depends on Vid_Qual
0xFD, // CHROMA GAIN CONTROL 2
0xFB, // LUMA GAIN CONTROL 1. Depends on Vid_Qual
0x58, // LUMA GAIN CONTROL 2
0x70, // MANUAL GAIN SHADOW CONTROL 1
0xFF, // MANUAL GAIN SHADOW CONTROL 2
0xE3, // MISC GAIN CONTROL. Update Gain once per field, 33-270 lines. PAL 133 NTSC 122, Color Kill Enabled
0x0F, // HSYNC POSITION CONTROL 1
0x01, // HSYNC POSITION CONTROL 2
0x00, // HSYNC POSITION CONTROL 3
0x00, // POLARITY CONTROL
};
#endif
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