adv7179.h

ADI的ADSP-BF561下实现PAL制式video的demo。

//AUTHOR: JC 	DATE: AUG 18TH, 2003
// Mod GJO Oct 28, 2003
#ifndef _ADV7179
#define _ADV7179

#define ADV7179WR	0x54
#define ADV7179RD	0x55
//#define ADV7179WR	0x56	//if ALSB =1
//#define ADV7179RD	0x57

enum ENCODER {	MODE_REGISTER_0 = 0x00,
			   	MODE_REGISTER_1,
			   	MODE_REGISTER_2,			   	
			   	MODE_REGISTER_3,			   	
			   	MODE_REGISTER_4,			   	
				RESERVED_0,
				RESERVED_1,				
				TIMER_REGISTER_0,
				TIMER_REGISTER_1,
				SFR_REGISTER_0,
				SFR_REGISTER_1,
				SFR_REGISTER_2,
				SFR_REGISTER_3,
				SPR_REGISTER,
				CCE_0_REGISTER,
				CCE_1_REGISTER,
				CCD_0_REGISTER,
				CCD_1_REGISTER,
				NTSC_PED_REG0_REGISTER,
				NTSC_PED_REG1_REGISTER,
				NTSC_PED_REG2_REGISTER ,
				NTSC_PED_REG3_REGISTER,
				CGMS_WSS_0_REGISTER,
				CGMS_WSS_1_REGISTER,
				CGMS_WSS_2_REGISTER,
				TELETEXT_REQ_REGISTER,
		   	};


//Mode Register 0

		   	
//Mode Register 1
#define COLOR_BAR_DISABLE				0x10
#define COLOR_BAR_ENABLE				0x90

//Mode Register 3
#define SVIDEO_DISABLE					0x00
#define SVIDEO_ENABLE					0x02

//Timer Register 0
#define BLANK_INPUT_ENABLE				0x00
#define BLANK_INPUT_DISABLE				0x08


volatile int DAC_Config[26] = {	
							0x00, 	// MODE0 REGISTER
							0x00, 	// MODE1 REGISTER
							0x00, 	// MODE2 REGISTER
							0x00, 	// MODE3 REGISTER
							0x02,	// MODE4 REGISTER
							0x00,	// RESERVED REGISTER
							0x00,	// RESERVED REGISTER
							0x08,	// TIMER 0 REGISTER
							0x00,	// TIMER 1 REGISTER
							0x16, 	// SFR 0 REGISTER
							0x7C, 	// SFR 1 REGISTER
							0xF0,	// SFR 2 REGISTER
							0x21,	// SFR 3 REGISTER
							0x00,	// SPR  REGISTER
							0x00, 	// CCE 0 REGISTER
							0x00, 	// CCE 1 REGISTER
							0x00,	// CCD 0 REGISTER
							0x00,	// CCD 1 REGISTER
							0x00,	// NTSC PED REG0 REGISTER
							0x00,	// NTSC PED REG1 REGISTER
							0x00,	// NTSC PED REG2 REGISTER 
							0x00,	// NTSC PED REG3 REGISTER
							0x00,	// CGMS_WSS_0 REGISTER
							0x00,	// CGMS_WSS_1 REGISTER
							0x00, 	// CGMS_WSS_2 REGISTER
							0x00, 	// TELETEXT REQ REGISTER
};

#endif